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[PATCH] skge: stop bogus sensor messages
Some versions of the Marvell yukon generate bogus sensor warning interrupts. The driver would flood log with these messages. Handle this situation cleanly by masking away at boot time. Fixes: http://bugs.gentoo.org/show_bug.cgi?id=87182 Signed-off-by: Stephen Hemminger <shemminger@osdl.org> drivers/net/skge.c | 24 ++++++++++-------------- drivers/net/skge.h | 8 ++++++-- 2 files changed, 16 insertions(+), 16 deletions(-) Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -2670,18 +2670,6 @@ static void skge_error_irq(struct skge_hw *hw)
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/* Timestamp (unused) overflow */
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if (hwstatus & IS_IRQ_TIST_OV)
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skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
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if (hwstatus & IS_IRQ_SENSOR) {
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/* no sensors on 32-bit Yukon */
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if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
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printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
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skge_write32(hw, B0_HWE_IMSK,
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IS_ERR_MSK & ~IS_IRQ_SENSOR);
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} else
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printk(KERN_WARNING PFX "sensor interrupt\n");
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}
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}
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if (hwstatus & IS_RAM_RD_PAR) {
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@ -2712,9 +2700,10 @@ static void skge_error_irq(struct skge_hw *hw)
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skge_pci_clear(hw);
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/* if error still set then just ignore it */
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hwstatus = skge_read32(hw, B0_HWE_ISRC);
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if (hwstatus & IS_IRQ_STAT) {
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printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
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pr_debug("IRQ status %x: still set ignoring hardware errors\n",
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hwstatus);
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hw->intr_mask &= ~IS_HW_ERR;
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}
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@ -2948,12 +2937,20 @@ static int skge_reset(struct skge_hw *hw)
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else
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hw->ram_size = t8 * 4096;
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hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_init(hw);
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else {
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/* switch power to VCC (WA for VAUX problem) */
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skge_write8(hw, B0_POWER_CTRL,
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PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
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/* avoid boards with stuck Hardware error bits */
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if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
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(skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
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printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
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hw->intr_mask &= ~IS_HW_ERR;
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}
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for (i = 0; i < hw->ports; i++) {
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skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
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skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
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@ -2994,7 +2991,6 @@ static int skge_reset(struct skge_hw *hw)
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skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
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skge_write32(hw, B2_IRQM_CTRL, TIM_START);
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hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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if (hw->chip_id != CHIP_ID_GENESIS)
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@ -214,8 +214,6 @@ enum {
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/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
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enum {
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IS_ERR_MSK = 0x00003fff,/* All Error bits */
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IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
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IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
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IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
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@ -230,6 +228,12 @@ enum {
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IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
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IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
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IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
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IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
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| IS_NO_STAT_M1 | IS_NO_STAT_M2
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| IS_RAM_RD_PAR | IS_RAM_WR_PAR
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| IS_M1_PAR_ERR | IS_M2_PAR_ERR
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| IS_R1_PAR_ERR | IS_R2_PAR_ERR,
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};
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/* B2_TST_CTRL1 8 bit Test Control Register 1 */
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