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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: dts: exynos: Use human-friendly symbols for interrupt properties in exynos5440
Replace hard-coded values of type of GIC interrupt and its flags with respective macros from header to increase code readability. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
parent
7184c42c57
commit
04a886727c
@ -10,6 +10,7 @@
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*/
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#include <dt-bindings/clock/exynos5440.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@ -42,7 +43,8 @@ gic: interrupt-controller@2E0000 {
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<0x2E2000 0x1000>,
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<0x2E4000 0x2000>,
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<0x2E6000 0x2000>;
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interrupts = <1 9 0xf04>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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cpus {
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@ -73,26 +75,26 @@ cpu@3 {
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arm-pmu {
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compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
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interrupts = <0 52 4>,
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<0 53 4>,
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<0 54 4>,
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<0 55 4>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <50000000>;
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};
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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operating-points = <
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/* KHz uV */
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1500000 1100000
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@ -109,7 +111,7 @@ cpufreq@160000 {
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serial_0: serial@B0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xB0000 0x1000>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -117,7 +119,7 @@ serial_0: serial@B0000 {
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serial_1: serial@C0000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0xC0000 0x1000>;
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interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -125,7 +127,7 @@ serial_1: serial@C0000 {
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spi_0: spi@D0000 {
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compatible = "samsung,exynos5440-spi";
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reg = <0xD0000 0x100>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,spi-src-clk = <0>;
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@ -137,14 +139,14 @@ spi_0: spi@D0000 {
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pin_ctrl: pinctrl@E0000 {
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compatible = "samsung,exynos5440-pinctrl";
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reg = <0xE0000 0x1000>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 42 IRQ_TYPE_LEVEL_HIGH>,
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<0 43 IRQ_TYPE_LEVEL_HIGH>,
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<0 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#gpio-cells = <2>;
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@ -169,7 +171,7 @@ uart1: uart1 {
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i2c@F0000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0xF0000 0x1000>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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@ -179,7 +181,7 @@ i2c@F0000 {
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i2c@100000 {
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compatible = "samsung,exynos5440-i2c";
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reg = <0x100000 0x1000>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clock CLK_B_125>;
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@ -189,7 +191,7 @@ i2c@100000 {
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watchdog@110000 {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x110000 0x1000>;
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interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "watchdog";
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};
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@ -198,7 +200,7 @@ gmac: ethernet@00230000 {
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compatible = "snps,dwmac-3.70a";
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reg = <0x00230000 0x8000>;
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interrupt-parent = <&gic>;
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interrupts = <0 31 4>;
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interrupts = <GIC_SPI 31 4>;
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interrupt-names = "macirq";
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phy-mode = "sgmii";
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clocks = <&clock CLK_GMAC0>;
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@ -216,8 +218,8 @@ amba {
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rtc@130000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x130000 0x1000>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "rtc";
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};
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@ -225,7 +227,7 @@ rtc@130000 {
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tmuctrl_0: tmuctrl@160118 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160118 0x230>, <0x160368 0x10>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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@ -234,7 +236,7 @@ tmuctrl_0: tmuctrl@160118 {
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tmuctrl_1: tmuctrl@16011C {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x16011C 0x230>, <0x160368 0x10>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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@ -243,7 +245,7 @@ tmuctrl_1: tmuctrl@16011C {
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tmuctrl_2: tmuctrl@160120 {
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compatible = "samsung,exynos5440-tmu";
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reg = <0x160120 0x230>, <0x160368 0x10>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_B_125>;
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clock-names = "tmu_apbif";
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#include "exynos5440-tmu-sensor-conf.dtsi"
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@ -267,7 +269,7 @@ cpu2_thermal: cpu2-thermal {
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sata@210000 {
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compatible = "snps,exynos5440-ahci";
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reg = <0x210000 0x10000>;
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interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_SATA>;
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clock-names = "sata";
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};
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@ -275,7 +277,7 @@ sata@210000 {
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ohci@220000 {
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compatible = "samsung,exynos5440-ohci";
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reg = <0x220000 0x1000>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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@ -283,7 +285,7 @@ ohci@220000 {
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ehci@221000 {
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compatible = "samsung,exynos5440-ehci";
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reg = <0x221000 0x1000>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_USB>;
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clock-names = "usbhost";
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};
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@ -293,9 +295,9 @@ pcie_0: pcie@290000 {
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reg = <0x290000 0x1000
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0x270000 0x1000
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0x271000 0x40>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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@ -316,9 +318,9 @@ pcie_1: pcie@2a0000 {
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reg = <0x2a0000 0x1000
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0x272000 0x1000
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0x271040 0x40>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 25 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
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clock-names = "pcie", "pcie_bus";
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#address-cells = <3>;
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