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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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spi/mcspi: allow configuration of pin directions
Allow D0 to be an input and D1 to be an output, configurable via platform data and a new DT property. Based on a patch from Matus Ujhelyi <matus.ujhelyi@streamunlimited.com> Signed-off-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -6,7 +6,9 @@ Required properties:
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- "ti,omap4-spi" for OMAP4+.
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- "ti,omap4-spi" for OMAP4+.
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- ti,spi-num-cs : Number of chipselect supported by the instance.
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- ti,spi-num-cs : Number of chipselect supported by the instance.
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- ti,hwmods: Name of the hwmod associated to the McSPI
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- ti,hwmods: Name of the hwmod associated to the McSPI
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- ti,pindir-d0-in-d1-out: Select the D0 pin as input and D1 as
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output. The default is D0 as output and
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D1 as input.
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Example:
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Example:
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@ -130,6 +130,7 @@ struct omap2_mcspi {
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struct omap2_mcspi_dma *dma_channels;
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struct omap2_mcspi_dma *dma_channels;
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struct device *dev;
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struct device *dev;
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struct omap2_mcspi_regs ctx;
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struct omap2_mcspi_regs ctx;
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unsigned int pin_dir:1;
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};
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};
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struct omap2_mcspi_cs {
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struct omap2_mcspi_cs {
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@ -765,8 +766,15 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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*/
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l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
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if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) {
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l |= OMAP2_MCSPI_CHCONF_DPE0;
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l &= ~OMAP2_MCSPI_CHCONF_IS;
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l &= ~OMAP2_MCSPI_CHCONF_DPE1;
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l |= OMAP2_MCSPI_CHCONF_DPE0;
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} else {
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l |= OMAP2_MCSPI_CHCONF_IS;
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l |= OMAP2_MCSPI_CHCONF_DPE1;
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l &= ~OMAP2_MCSPI_CHCONF_DPE0;
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}
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/* wordlength */
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/* wordlength */
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l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
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l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
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@ -1167,6 +1175,11 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
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master->cleanup = omap2_mcspi_cleanup;
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master->cleanup = omap2_mcspi_cleanup;
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master->dev.of_node = node;
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master->dev.of_node = node;
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dev_set_drvdata(&pdev->dev, master);
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mcspi = spi_master_get_devdata(master);
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mcspi->master = master;
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match = of_match_device(omap_mcspi_of_match, &pdev->dev);
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match = of_match_device(omap_mcspi_of_match, &pdev->dev);
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if (match) {
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if (match) {
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u32 num_cs = 1; /* default number of chipselect */
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u32 num_cs = 1; /* default number of chipselect */
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@ -1175,19 +1188,17 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
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of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
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of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
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master->num_chipselect = num_cs;
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master->num_chipselect = num_cs;
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master->bus_num = bus_num++;
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master->bus_num = bus_num++;
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if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL))
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mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
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} else {
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} else {
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pdata = pdev->dev.platform_data;
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pdata = pdev->dev.platform_data;
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master->num_chipselect = pdata->num_cs;
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master->num_chipselect = pdata->num_cs;
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if (pdev->id != -1)
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if (pdev->id != -1)
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master->bus_num = pdev->id;
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master->bus_num = pdev->id;
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mcspi->pin_dir = pdata->pin_dir;
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}
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}
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regs_offset = pdata->regs_offset;
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regs_offset = pdata->regs_offset;
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dev_set_drvdata(&pdev->dev, master);
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mcspi = spi_master_get_devdata(master);
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mcspi->master = master;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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if (r == NULL) {
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status = -ENODEV;
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status = -ENODEV;
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@ -7,9 +7,13 @@
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#define OMAP4_MCSPI_REG_OFFSET 0x100
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#define OMAP4_MCSPI_REG_OFFSET 0x100
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#define MCSPI_PINDIR_D0_OUT_D1_IN 0
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#define MCSPI_PINDIR_D0_IN_D1_OUT 1
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struct omap2_mcspi_platform_config {
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struct omap2_mcspi_platform_config {
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unsigned short num_cs;
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unsigned short num_cs;
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unsigned int regs_offset;
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unsigned int regs_offset;
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unsigned int pin_dir:1;
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};
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};
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struct omap2_mcspi_dev_attr {
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struct omap2_mcspi_dev_attr {
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