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clk: sunxi-ng: add support for suniv F1C100s SoC
The suniv F1C100s SoC (the chip in some new F-series products of Allwinner) has a CCU which seems to be a stripped version of the CCU in SoCs after sun6i. Add support for the CCU. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Mesih Kilinc
Maxime Ripard
parent
3d737ddbe7
commit
0380126eb9
@ -6,6 +6,11 @@ config SUNXI_CCU
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if SUNXI_CCU
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config SUNIV_F1C100S_CCU
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bool "Support for the Allwinner newer F1C100s CCU"
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default MACH_SUNIV
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depends on MACH_SUNIV || COMPILE_TEST
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config SUN50I_A64_CCU
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bool "Support for the Allwinner A64 CCU"
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default ARM64 && ARCH_SUNXI
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@ -21,6 +21,7 @@ obj-y += ccu_nm.o
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obj-y += ccu_mp.o
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# SoC support
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obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
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obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
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obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
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obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
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541
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
Normal file
541
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
Normal file
@ -0,0 +1,541 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io>
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_mult.h"
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#include "ccu_nk.h"
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#include "ccu_nkm.h"
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#include "ccu_nkmp.h"
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#include "ccu_nm.h"
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#include "ccu_phase.h"
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#include "ccu-suniv-f1c100s.h"
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static struct ccu_nkmp pll_cpu_clk = {
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.enable = BIT(31),
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.lock = BIT(28),
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.n = _SUNXI_CCU_MULT(8, 5),
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.k = _SUNXI_CCU_MULT(4, 2),
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.m = _SUNXI_CCU_DIV(0, 2),
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/* MAX is guessed by the BSP table */
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.p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
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.common = {
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.reg = 0x000,
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.hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
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&ccu_nkmp_ops,
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CLK_SET_RATE_UNGATE),
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},
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};
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/*
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* The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
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* the base (2x, 4x and 8x), and one variable divider (the one true
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* pll audio).
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*
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* We don't have any need for the variable divider for now, so we just
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* hardcode it to match with the clock names
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*/
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#define SUNIV_PLL_AUDIO_REG 0x008
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static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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"osc24M", 0x008,
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8, 7, /* N */
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0, 5, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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"osc24M", 0x010,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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"osc24M", 0x018,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
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"osc24M", 0x020,
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8, 5, /* N */
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4, 2, /* K */
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0, 2, /* M */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_IS_CRITICAL);
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static struct ccu_nk pll_periph_clk = {
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.enable = BIT(31),
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.lock = BIT(28),
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.k = _SUNXI_CCU_MULT(4, 2),
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.n = _SUNXI_CCU_MULT(8, 5),
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.common = {
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.reg = 0x028,
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.hw.init = CLK_HW_INIT("pll-periph", "osc24M",
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&ccu_nk_ops, 0),
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},
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};
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static const char * const cpu_parents[] = { "osc32k", "osc24M",
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"pll-cpu", "pll-cpu" };
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static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
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0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
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static const char * const ahb_parents[] = { "osc32k", "osc24M",
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"cpu", "pll-periph" };
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static const struct ccu_mux_var_prediv ahb_predivs[] = {
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{ .index = 3, .shift = 6, .width = 2 },
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};
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static struct ccu_div ahb_clk = {
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.div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
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.mux = {
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.shift = 12,
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.width = 2,
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.var_predivs = ahb_predivs,
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.n_var_predivs = ARRAY_SIZE(ahb_predivs),
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},
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.common = {
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.reg = 0x054,
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.features = CCU_FEATURE_VARIABLE_PREDIV,
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.hw.init = CLK_HW_INIT_PARENTS("ahb",
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ahb_parents,
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&ccu_div_ops,
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0),
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},
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};
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static struct clk_div_table apb_div_table[] = {
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{ .val = 0, .div = 2 },
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{ .val = 1, .div = 2 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 8 },
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{ /* Sentinel */ },
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};
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static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
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0x054, 8, 2, apb_div_table, 0);
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static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb",
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0x060, BIT(6), 0);
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static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
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0x060, BIT(8), 0);
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static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
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0x060, BIT(9), 0);
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static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
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0x060, BIT(14), 0);
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static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
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0x060, BIT(20), 0);
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static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
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0x060, BIT(21), 0);
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static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
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0x060, BIT(24), 0);
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static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
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0x064, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
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0x064, BIT(4), 0);
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static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
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0x064, BIT(5), 0);
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static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
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0x064, BIT(8), 0);
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static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
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0x064, BIT(9), 0);
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static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
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0x064, BIT(10), 0);
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static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
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0x064, BIT(12), 0);
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static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
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0x064, BIT(14), 0);
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static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
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0x068, BIT(0), 0);
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static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
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0x068, BIT(1), 0);
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static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
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0x068, BIT(2), 0);
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static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
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0x068, BIT(3), 0);
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static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
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0x068, BIT(12), 0);
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static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
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0x068, BIT(16), 0);
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static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
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0x068, BIT(17), 0);
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static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
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0x068, BIT(18), 0);
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static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
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0x068, BIT(19), 0);
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static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
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0x068, BIT(20), 0);
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static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
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0x068, BIT(21), 0);
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static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
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0x068, BIT(22), 0);
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static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
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0x088, 20, 3, 0);
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static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
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0x088, 8, 3, 0);
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static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
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0, 4, /* M */
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16, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
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0x08c, 20, 3, 0);
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static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
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0x08c, 8, 3, 0);
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static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
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"pll-audio-4x",
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"pll-audio-2x",
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"pll-audio" };
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static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
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0x0b0, 16, 2, BIT(31), 0);
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static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
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0x0b4, 16, 2, BIT(31), 0);
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/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
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static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
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0x0cc, BIT(8), 0);
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static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
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0x100, BIT(0), 0);
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static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
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0x100, BIT(1), 0);
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static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
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"pll-ddr", 0x100, BIT(2), 0);
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static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
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0x100, BIT(3), 0);
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static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
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0x100, BIT(24), 0);
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static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
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0x100, BIT(26), 0);
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static const char * const de_parents[] = { "pll-video", "pll-periph" };
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static const u8 de_table[] = { 0, 2, };
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static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
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de_parents, de_table,
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0x104, 0, 4, 24, 3, BIT(31), 0);
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static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
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de_parents, de_table,
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0x10c, 0, 4, 24, 3, BIT(31), 0);
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static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
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static const u8 tcon_table[] = { 0, 2, };
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static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
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tcon_parents, tcon_table,
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0x118, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static const char * const deinterlace_parents[] = { "pll-video",
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"pll-video-2x" };
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static const u8 deinterlace_table[] = { 0, 2, };
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static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
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deinterlace_parents, deinterlace_table,
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0x11c, 0, 4, 24, 3, BIT(31), 0);
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static const char * const tve_clk2_parents[] = { "pll-video",
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"pll-video-2x" };
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static const u8 tve_clk2_table[] = { 0, 2, };
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static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
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tve_clk2_parents, tve_clk2_table,
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0x120, 0, 4, 24, 3, BIT(31), 0);
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static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
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0x120, 8, 1, BIT(15), 0);
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static const char * const tvd_parents[] = { "pll-video", "osc24M",
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"pll-video-2x" };
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static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
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0x124, 0, 4, 24, 3, BIT(31), 0);
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static const char * const csi_parents[] = { "pll-video", "osc24M" };
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static const u8 csi_table[] = { 0, 5, };
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static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
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0x120, 0, 4, 8, 3, BIT(15), 0);
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/*
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* TODO: BSP says the parent is pll-audio, however common sense and experience
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* told us it should be pll-ve. pll-ve is totally not used in BSP code.
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*/
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static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
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static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
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static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
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static struct ccu_common *suniv_ccu_clks[] = {
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&pll_cpu_clk.common,
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&pll_audio_base_clk.common,
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&pll_video_clk.common,
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&pll_ve_clk.common,
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&pll_ddr0_clk.common,
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&pll_periph_clk.common,
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&cpu_clk.common,
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&ahb_clk.common,
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&apb_clk.common,
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&bus_dma_clk.common,
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&bus_mmc0_clk.common,
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&bus_mmc1_clk.common,
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&bus_dram_clk.common,
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&bus_spi0_clk.common,
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&bus_spi1_clk.common,
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&bus_otg_clk.common,
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&bus_ve_clk.common,
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&bus_lcd_clk.common,
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&bus_deinterlace_clk.common,
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&bus_csi_clk.common,
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&bus_tve_clk.common,
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&bus_tvd_clk.common,
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&bus_de_be_clk.common,
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&bus_de_fe_clk.common,
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&bus_codec_clk.common,
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&bus_spdif_clk.common,
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&bus_ir_clk.common,
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&bus_rsb_clk.common,
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&bus_i2s0_clk.common,
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&bus_i2c0_clk.common,
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&bus_i2c1_clk.common,
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&bus_i2c2_clk.common,
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&bus_pio_clk.common,
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&bus_uart0_clk.common,
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&bus_uart1_clk.common,
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&bus_uart2_clk.common,
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&mmc0_clk.common,
|
||||
&mmc0_sample_clk.common,
|
||||
&mmc0_output_clk.common,
|
||||
&mmc1_clk.common,
|
||||
&mmc1_sample_clk.common,
|
||||
&mmc1_output_clk.common,
|
||||
&i2s_clk.common,
|
||||
&spdif_clk.common,
|
||||
&usb_phy0_clk.common,
|
||||
&dram_ve_clk.common,
|
||||
&dram_csi_clk.common,
|
||||
&dram_deinterlace_clk.common,
|
||||
&dram_tvd_clk.common,
|
||||
&dram_de_fe_clk.common,
|
||||
&dram_de_be_clk.common,
|
||||
&de_be_clk.common,
|
||||
&de_fe_clk.common,
|
||||
&tcon_clk.common,
|
||||
&deinterlace_clk.common,
|
||||
&tve_clk2_clk.common,
|
||||
&tve_clk1_clk.common,
|
||||
&tvd_clk.common,
|
||||
&csi_clk.common,
|
||||
&ve_clk.common,
|
||||
&codec_clk.common,
|
||||
&avs_clk.common,
|
||||
};
|
||||
|
||||
static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
|
||||
"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
|
||||
"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
|
||||
"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
|
||||
"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
|
||||
static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
|
||||
"pll-video", 1, 2, 0);
|
||||
|
||||
static struct clk_hw_onecell_data suniv_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
|
||||
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
|
||||
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
|
||||
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
|
||||
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
|
||||
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
|
||||
[CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
|
||||
[CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
|
||||
[CLK_PLL_VE] = &pll_ve_clk.common.hw,
|
||||
[CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
|
||||
[CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
|
||||
[CLK_CPU] = &cpu_clk.common.hw,
|
||||
[CLK_AHB] = &ahb_clk.common.hw,
|
||||
[CLK_APB] = &apb_clk.common.hw,
|
||||
[CLK_BUS_DMA] = &bus_dma_clk.common.hw,
|
||||
[CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
|
||||
[CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
|
||||
[CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
|
||||
[CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
|
||||
[CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
|
||||
[CLK_BUS_OTG] = &bus_otg_clk.common.hw,
|
||||
[CLK_BUS_VE] = &bus_ve_clk.common.hw,
|
||||
[CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
|
||||
[CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
|
||||
[CLK_BUS_CSI] = &bus_csi_clk.common.hw,
|
||||
[CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
|
||||
[CLK_BUS_TVE] = &bus_tve_clk.common.hw,
|
||||
[CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
|
||||
[CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
|
||||
[CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
|
||||
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
|
||||
[CLK_BUS_IR] = &bus_ir_clk.common.hw,
|
||||
[CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
|
||||
[CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
|
||||
[CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
|
||||
[CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
|
||||
[CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
|
||||
[CLK_BUS_PIO] = &bus_pio_clk.common.hw,
|
||||
[CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
|
||||
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
|
||||
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
|
||||
[CLK_MMC0] = &mmc0_clk.common.hw,
|
||||
[CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
|
||||
[CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
|
||||
[CLK_MMC1] = &mmc1_clk.common.hw,
|
||||
[CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
|
||||
[CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
|
||||
[CLK_I2S] = &i2s_clk.common.hw,
|
||||
[CLK_SPDIF] = &spdif_clk.common.hw,
|
||||
[CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
|
||||
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
|
||||
[CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
|
||||
[CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
|
||||
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
|
||||
[CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
|
||||
[CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
|
||||
[CLK_DE_BE] = &de_be_clk.common.hw,
|
||||
[CLK_DE_FE] = &de_fe_clk.common.hw,
|
||||
[CLK_TCON] = &tcon_clk.common.hw,
|
||||
[CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
|
||||
[CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
|
||||
[CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
|
||||
[CLK_TVD] = &tvd_clk.common.hw,
|
||||
[CLK_CSI] = &csi_clk.common.hw,
|
||||
[CLK_VE] = &ve_clk.common.hw,
|
||||
[CLK_CODEC] = &codec_clk.common.hw,
|
||||
[CLK_AVS] = &avs_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER,
|
||||
};
|
||||
|
||||
static struct ccu_reset_map suniv_ccu_resets[] = {
|
||||
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
|
||||
|
||||
[RST_BUS_DMA] = { 0x2c0, BIT(6) },
|
||||
[RST_BUS_MMC0] = { 0x2c0, BIT(8) },
|
||||
[RST_BUS_MMC1] = { 0x2c0, BIT(9) },
|
||||
[RST_BUS_DRAM] = { 0x2c0, BIT(14) },
|
||||
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
|
||||
[RST_BUS_SPI1] = { 0x2c0, BIT(21) },
|
||||
[RST_BUS_OTG] = { 0x2c0, BIT(24) },
|
||||
[RST_BUS_VE] = { 0x2c4, BIT(0) },
|
||||
[RST_BUS_LCD] = { 0x2c4, BIT(4) },
|
||||
[RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
|
||||
[RST_BUS_CSI] = { 0x2c4, BIT(8) },
|
||||
[RST_BUS_TVD] = { 0x2c4, BIT(9) },
|
||||
[RST_BUS_TVE] = { 0x2c4, BIT(10) },
|
||||
[RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
|
||||
[RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
|
||||
[RST_BUS_CODEC] = { 0x2d0, BIT(0) },
|
||||
[RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
|
||||
[RST_BUS_IR] = { 0x2d0, BIT(2) },
|
||||
[RST_BUS_RSB] = { 0x2d0, BIT(3) },
|
||||
[RST_BUS_I2S0] = { 0x2d0, BIT(12) },
|
||||
[RST_BUS_I2C0] = { 0x2d0, BIT(16) },
|
||||
[RST_BUS_I2C1] = { 0x2d0, BIT(17) },
|
||||
[RST_BUS_I2C2] = { 0x2d0, BIT(18) },
|
||||
[RST_BUS_UART0] = { 0x2d0, BIT(20) },
|
||||
[RST_BUS_UART1] = { 0x2d0, BIT(21) },
|
||||
[RST_BUS_UART2] = { 0x2d0, BIT(22) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc suniv_ccu_desc = {
|
||||
.ccu_clks = suniv_ccu_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks),
|
||||
|
||||
.hw_clks = &suniv_hw_clks,
|
||||
|
||||
.resets = suniv_ccu_resets,
|
||||
.num_resets = ARRAY_SIZE(suniv_ccu_resets),
|
||||
};
|
||||
|
||||
static struct ccu_pll_nb suniv_pll_cpu_nb = {
|
||||
.common = &pll_cpu_clk.common,
|
||||
/* copy from pll_cpu_clk */
|
||||
.enable = BIT(31),
|
||||
.lock = BIT(28),
|
||||
};
|
||||
|
||||
static struct ccu_mux_nb suniv_cpu_nb = {
|
||||
.common = &cpu_clk.common,
|
||||
.cm = &cpu_clk.mux,
|
||||
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
|
||||
.bypass_index = 1, /* index of 24 MHz oscillator */
|
||||
};
|
||||
|
||||
static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
|
||||
{
|
||||
void __iomem *reg;
|
||||
u32 val;
|
||||
|
||||
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(reg)) {
|
||||
pr_err("%pOF: Could not map the clock registers\n", node);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Force the PLL-Audio-1x divider to 4 */
|
||||
val = readl(reg + SUNIV_PLL_AUDIO_REG);
|
||||
val &= ~GENMASK(19, 16);
|
||||
writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
|
||||
|
||||
sunxi_ccu_probe(node, reg, &suniv_ccu_desc);
|
||||
|
||||
/* Gate then ungate PLL CPU after any rate changes */
|
||||
ccu_pll_notifier_register(&suniv_pll_cpu_nb);
|
||||
|
||||
/* Reparent CPU during PLL CPU rate changes */
|
||||
ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
|
||||
&suniv_cpu_nb);
|
||||
}
|
||||
CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu",
|
||||
suniv_f1c100s_ccu_setup);
|
||||
34
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
Normal file
34
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
Normal file
@ -0,0 +1,34 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CCU_SUNIV_F1C100S_H_
|
||||
#define _CCU_SUNIV_F1C100S_H_
|
||||
|
||||
#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
|
||||
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
|
||||
|
||||
#define CLK_PLL_CPU 0
|
||||
#define CLK_PLL_AUDIO_BASE 1
|
||||
#define CLK_PLL_AUDIO 2
|
||||
#define CLK_PLL_AUDIO_2X 3
|
||||
#define CLK_PLL_AUDIO_4X 4
|
||||
#define CLK_PLL_AUDIO_8X 5
|
||||
#define CLK_PLL_VIDEO 6
|
||||
#define CLK_PLL_VIDEO_2X 7
|
||||
#define CLK_PLL_VE 8
|
||||
#define CLK_PLL_DDR0 9
|
||||
#define CLK_PLL_PERIPH 10
|
||||
|
||||
/* CPU clock is exported */
|
||||
|
||||
#define CLK_AHB 12
|
||||
#define CLK_APB 13
|
||||
|
||||
/* All bus gates, DRAM gates and mod clocks are exported */
|
||||
|
||||
#define CLK_NUMBER (CLK_AVS + 1)
|
||||
|
||||
#endif /* _CCU_SUNIV_F1C100S_H_ */
|
||||
Loading…
Reference in New Issue
Block a user