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drm/i915: Clear the pending_gpu_fenced_access flag at the start of execbuffer
Otherwise once we use the buffer with a BLT command on gen2/3, we will always regard future command submissions as continuing the fenced access. However, now that we flush/invalidate between every batch we can drop this pessimism. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -413,6 +413,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
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obj->base.pending_read_domains = 0;
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obj->base.pending_write_domain = 0;
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obj->pending_fenced_gpu_access = false;
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}
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list_splice(&ordered_objects, objects);
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