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x86: Clarify/fix no-op barriers for text_poke_bp()
So I was looking at text_poke_bp() today and I couldn't make sense of the barriers there. How's for something like so? Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Acked-by: Jiri Kosina <jkosina@suse.cz> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: masami.hiramatsu.pt@hitachi.com Link: http://lkml.kernel.org/r/20170731102154.f57cvkjtnbmtctk6@hirez.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -742,7 +742,16 @@ static void *bp_int3_handler, *bp_int3_addr;
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int poke_int3_handler(struct pt_regs *regs)
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{
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/* bp_patching_in_progress */
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/*
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* Having observed our INT3 instruction, we now must observe
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* bp_patching_in_progress.
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*
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* in_progress = TRUE INT3
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* WMB RMB
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* write INT3 if (in_progress)
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*
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* Idem for bp_int3_handler.
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*/
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smp_rmb();
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if (likely(!bp_patching_in_progress))
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@ -788,9 +797,8 @@ void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
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bp_int3_addr = (u8 *)addr + sizeof(int3);
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bp_patching_in_progress = true;
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/*
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* Corresponding read barrier in int3 notifier for
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* making sure the in_progress flags is correctly ordered wrt.
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* patching
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* Corresponding read barrier in int3 notifier for making sure the
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* in_progress and handler are correctly ordered wrt. patching.
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*/
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smp_wmb();
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@ -815,9 +823,11 @@ void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
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text_poke(addr, opcode, sizeof(int3));
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on_each_cpu(do_sync_core, NULL, 1);
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/*
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* sync_core() implies an smp_mb() and orders this store against
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* the writing of the new instruction.
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*/
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bp_patching_in_progress = false;
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smp_wmb();
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return addr;
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}
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