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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'topic/dw' into for-linus
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010299bfc2
@ -27,6 +27,10 @@ Optional properties:
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general purpose DMA channel allocator. False if not passed.
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- multi-block: Multi block transfers supported by hardware. Array property with
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one cell per channel. 0: not supported, 1 (default): supported.
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- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
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The default value is 0 (for non-cacheable, non-buffered,
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unprivileged data access).
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Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
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Example:
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@ -14363,9 +14363,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
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M: Viresh Kumar <vireshk@kernel.org>
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R: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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S: Maintained
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F: Documentation/devicetree/bindings/dma/snps-dma.txt
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F: drivers/dma/dw/
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F: include/dt-bindings/dma/dw-dmac.h
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F: include/linux/dma/dw.h
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F: include/linux/platform_data/dma-dw.h
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F: drivers/dma/dw/
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SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER
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M: Jose Abreu <Jose.Abreu@synopsys.com>
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@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
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static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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u32 cfghi = DWC_CFGH_FIFO_MODE;
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u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
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bool hs_polarity = dwc->dws.hs_polarity;
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cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
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cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
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cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
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/* Set polarity of handshake interface */
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cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
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@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
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pdata->multi_block[tmp] = 1;
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}
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if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
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if (tmp > CHAN_PROTCTL_MASK)
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return NULL;
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pdata->protctl = tmp;
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}
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return pdata;
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}
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#else
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@ -200,6 +200,10 @@ enum dw_dma_msize {
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_PROTCTL_DATA (0 << 2) /* data access - always set */
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#define DWC_CFGH_PROTCTL_PRIV (1 << 2) /* privileged -> AHB HPROT[1] */
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#define DWC_CFGH_PROTCTL_BUFFER (2 << 2) /* bufferable -> AHB HPROT[2] */
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#define DWC_CFGH_PROTCTL_CACHE (4 << 2) /* cacheable -> AHB HPROT[3] */
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#define DWC_CFGH_DS_UPD_EN (1 << 5)
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#define DWC_CFGH_SS_UPD_EN (1 << 6)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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14
include/dt-bindings/dma/dw-dmac.h
Normal file
14
include/dt-bindings/dma/dw-dmac.h
Normal file
@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
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#define __DT_BINDINGS_DMA_DW_DMAC_H__
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/*
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* Protection Control bits provide protection against illegal transactions.
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* The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
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*/
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#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */
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#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
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#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
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#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */
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@ -49,6 +49,7 @@ struct dw_dma_slave {
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* @data_width: Maximum data width supported by hardware per AHB master
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* (in bytes, power of 2)
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* @multi_block: Multi block transfers supported by hardware per channel.
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* @protctl: Protection control signals setting per channel.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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@ -65,6 +66,11 @@ struct dw_dma_platform_data {
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unsigned char nr_masters;
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unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
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#define CHAN_PROTCTL_PRIVILEGED BIT(0)
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#define CHAN_PROTCTL_BUFFERABLE BIT(1)
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#define CHAN_PROTCTL_CACHEABLE BIT(2)
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#define CHAN_PROTCTL_MASK GENMASK(2, 0)
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unsigned char protctl;
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};
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#endif /* _PLATFORM_DATA_DMA_DW_H */
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