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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -347,7 +347,8 @@ nand: nand@68000000 {
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand2cs>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -394,7 +394,8 @@ nand: nand@68000000 {
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -439,7 +439,8 @@ nand: nand@68000000 {
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand2cs>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -531,7 +531,8 @@ nand: nand@68000000 {
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand2cs>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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@ -351,7 +351,8 @@ nand: nand@68000000 {
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand2cs>;
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clocks = <&sys_clk 2>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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resets = <&sys_rst 2>;
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};
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};
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