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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: shmobile: r7s72100: sort dtsi file by address
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
parent
6a8663f8bb
commit
005980c002
@ -52,16 +52,6 @@ usb_x1_clk: usb_x1_clk {
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clock-output-names = "usb_x1";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-cpg-clocks",
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"renesas,rz-cpg-clocks";
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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};
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/* Fixed factor clocks */
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b_clk: b_clk {
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#clock-cells = <0>;
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@ -88,6 +78,16 @@ p0_clk: p0_clk {
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clock-output-names = "p0";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-cpg-clocks",
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"renesas,rz-cpg-clocks";
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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};
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/* MSTP clocks */
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mstp3_clks: mstp3_clks@fcfe0420 {
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#clock-cells = <1>;
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@ -148,97 +148,6 @@ cpu@0 {
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};
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};
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gic: interrupt-controller@e8201000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8201000 0x1000>,
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<0xe8202000 0x1000>;
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};
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i2c0: i2c@fcfee000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee000 0x44>;
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interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
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<0 158 IRQ_TYPE_EDGE_RISING>,
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<0 159 IRQ_TYPE_EDGE_RISING>,
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<0 160 IRQ_TYPE_LEVEL_HIGH>,
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<0 161 IRQ_TYPE_LEVEL_HIGH>,
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<0 162 IRQ_TYPE_LEVEL_HIGH>,
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<0 163 IRQ_TYPE_LEVEL_HIGH>,
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<0 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@fcfee400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee400 0x44>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
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<0 166 IRQ_TYPE_EDGE_RISING>,
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<0 167 IRQ_TYPE_EDGE_RISING>,
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<0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 169 IRQ_TYPE_LEVEL_HIGH>,
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<0 170 IRQ_TYPE_LEVEL_HIGH>,
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<0 171 IRQ_TYPE_LEVEL_HIGH>,
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<0 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c2: i2c@fcfee800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee800 0x44>;
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interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
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<0 174 IRQ_TYPE_EDGE_RISING>,
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<0 175 IRQ_TYPE_EDGE_RISING>,
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<0 176 IRQ_TYPE_LEVEL_HIGH>,
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<0 177 IRQ_TYPE_LEVEL_HIGH>,
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<0 178 IRQ_TYPE_LEVEL_HIGH>,
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<0 179 IRQ_TYPE_LEVEL_HIGH>,
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<0 180 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c3: i2c@fcfeec00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfeec00 0x44>;
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interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
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<0 182 IRQ_TYPE_EDGE_RISING>,
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<0 183 IRQ_TYPE_EDGE_RISING>,
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<0 184 IRQ_TYPE_LEVEL_HIGH>,
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<0 185 IRQ_TYPE_LEVEL_HIGH>,
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<0 186 IRQ_TYPE_LEVEL_HIGH>,
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<0 187 IRQ_TYPE_LEVEL_HIGH>,
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<0 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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status = "disabled";
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};
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scif0: serial@e8007000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007000 64>;
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@ -404,4 +313,95 @@ spi4: spi@e800e800 {
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#size-cells = <0>;
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status = "disabled";
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};
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gic: interrupt-controller@e8201000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8201000 0x1000>,
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<0xe8202000 0x1000>;
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};
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i2c0: i2c@fcfee000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee000 0x44>;
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interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
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<0 158 IRQ_TYPE_EDGE_RISING>,
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<0 159 IRQ_TYPE_EDGE_RISING>,
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<0 160 IRQ_TYPE_LEVEL_HIGH>,
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<0 161 IRQ_TYPE_LEVEL_HIGH>,
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<0 162 IRQ_TYPE_LEVEL_HIGH>,
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<0 163 IRQ_TYPE_LEVEL_HIGH>,
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<0 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@fcfee400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee400 0x44>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
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<0 166 IRQ_TYPE_EDGE_RISING>,
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<0 167 IRQ_TYPE_EDGE_RISING>,
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<0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 169 IRQ_TYPE_LEVEL_HIGH>,
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<0 170 IRQ_TYPE_LEVEL_HIGH>,
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<0 171 IRQ_TYPE_LEVEL_HIGH>,
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<0 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c2: i2c@fcfee800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee800 0x44>;
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interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
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<0 174 IRQ_TYPE_EDGE_RISING>,
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<0 175 IRQ_TYPE_EDGE_RISING>,
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<0 176 IRQ_TYPE_LEVEL_HIGH>,
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<0 177 IRQ_TYPE_LEVEL_HIGH>,
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<0 178 IRQ_TYPE_LEVEL_HIGH>,
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<0 179 IRQ_TYPE_LEVEL_HIGH>,
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<0 180 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c3: i2c@fcfeec00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfeec00 0x44>;
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interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
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<0 182 IRQ_TYPE_EDGE_RISING>,
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<0 183 IRQ_TYPE_EDGE_RISING>,
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<0 184 IRQ_TYPE_LEVEL_HIGH>,
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<0 185 IRQ_TYPE_LEVEL_HIGH>,
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<0 186 IRQ_TYPE_LEVEL_HIGH>,
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<0 187 IRQ_TYPE_LEVEL_HIGH>,
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<0 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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status = "disabled";
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};
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};
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