mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 16:36:43 +07:00
mt76: mt76x2: implement full device restart on watchdog reset
Restart the firmware and re-initialize the MAC to be able to recover from more kinds of hang states Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
de3c2af15f
commit
004960423f
@ -144,6 +144,7 @@ struct mt76_mcu_ops {
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const struct mt76_reg_pair *rp, int len);
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int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
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struct mt76_reg_pair *rp, int len);
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int (*mcu_restart)(struct mt76_dev *dev);
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};
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struct mt76_queue_ops {
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@ -67,6 +67,32 @@ int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
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}
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EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup);
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void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
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struct ieee80211_key_conf *key)
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{
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enum mt76x02_cipher_type cipher;
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u8 key_data[32];
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u32 iv, eiv;
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u64 pn;
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cipher = mt76x02_mac_get_key_info(key, key_data);
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iv = mt76_rr(dev, MT_WCID_IV(idx));
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eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4);
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pn = (u64)eiv << 16;
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if (cipher == MT_CIPHER_TKIP) {
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pn |= (iv >> 16) & 0xff;
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pn |= (iv & 0xff) << 8;
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} else if (cipher >= MT_CIPHER_AES_CCMP) {
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pn |= iv & 0xffff;
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} else {
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return;
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}
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atomic64_set(&key->tx_pn, pn);
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}
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int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
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struct ieee80211_key_conf *key)
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{
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@ -177,6 +177,8 @@ int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
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u8 key_idx, struct ieee80211_key_conf *key);
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int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
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struct ieee80211_key_conf *key);
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void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
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struct ieee80211_key_conf *key);
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void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx,
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u8 *mac);
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void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop);
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@ -19,6 +19,7 @@
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#include <linux/irq.h>
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#include "mt76x02.h"
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#include "mt76x02_mcu.h"
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#include "mt76x02_trace.h"
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struct beacon_bc_data {
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@ -418,9 +419,65 @@ static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
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return i < 4;
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}
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static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key, void *data)
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{
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struct mt76x02_dev *dev = hw->priv;
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struct mt76_wcid *wcid;
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if (!sta)
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return;
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wcid = (struct mt76_wcid *) sta->drv_priv;
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if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
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return;
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mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
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}
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static void mt76x02_reset_state(struct mt76x02_dev *dev)
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{
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int i;
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clear_bit(MT76_STATE_RUNNING, &dev->mt76.state);
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rcu_read_lock();
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ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.wcid); i++) {
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struct mt76_wcid *wcid = rcu_dereference(dev->mt76.wcid[i]);
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struct mt76x02_sta *msta;
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struct ieee80211_sta *sta;
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struct ieee80211_vif *vif;
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void *priv;
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if (!wcid)
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continue;
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priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
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sta = container_of(priv, struct ieee80211_sta, drv_priv);
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priv = msta->vif;
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vif = container_of(priv, struct ieee80211_vif, drv_priv);
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mt76_sta_state(dev->mt76.hw, vif, sta,
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IEEE80211_STA_NONE, IEEE80211_STA_NOTEXIST);
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memset(msta, 0, sizeof(*msta));
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}
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rcu_read_unlock();
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dev->vif_mask = 0;
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dev->beacon_mask = 0;
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}
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static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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{
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u32 mask = dev->mt76.mmio.irqmask;
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bool restart = dev->mt76.mcu_ops->mcu_restart;
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int i;
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ieee80211_stop_queues(dev->mt76.hw);
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@ -432,6 +489,9 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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for (i = 0; i < ARRAY_SIZE(dev->mt76.napi); i++)
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napi_disable(&dev->mt76.napi[i]);
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if (restart)
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mt76x02_reset_state(dev);
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mutex_lock(&dev->mt76.mutex);
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if (dev->beacon_mask)
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@ -452,20 +512,21 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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/* let fw reset DMA */
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mt76_set(dev, 0x734, 0x3);
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if (restart)
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dev->mt76.mcu_ops->mcu_restart(&dev->mt76);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.q_tx); i++)
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mt76_queue_tx_cleanup(dev, i, true);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.q_rx); i++)
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mt76_queue_rx_reset(dev, i);
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mt76_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
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mt76_set(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
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mt76x02_mac_start(dev);
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if (dev->ed_monitor)
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mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
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if (dev->beacon_mask)
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if (dev->beacon_mask && !restart)
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mt76_set(dev, MT_BEACON_TIME_CFG,
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MT_BEACON_TIME_CFG_BEACON_TX |
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MT_BEACON_TIME_CFG_TBTT_EN);
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@ -486,9 +547,13 @@ static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
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napi_schedule(&dev->mt76.napi[i]);
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}
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ieee80211_wake_queues(dev->mt76.hw);
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mt76_txq_schedule_all(&dev->mt76);
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if (restart) {
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mt76x02_mcu_function_select(dev, Q_SELECT, 1);
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ieee80211_restart_hw(dev->mt76.hw);
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} else {
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ieee80211_wake_queues(dev->mt76.hw);
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mt76_txq_schedule_all(&dev->mt76);
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}
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}
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static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
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@ -237,6 +237,8 @@ int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
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struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
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int idx = 0;
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memset(msta, 0, sizeof(*msta));
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idx = mt76_wcid_alloc(dev->mt76.wcid_mask, ARRAY_SIZE(dev->mt76.wcid));
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if (idx < 0)
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return -ENOSPC;
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@ -274,6 +276,8 @@ mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif,
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struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
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struct mt76_txq *mtxq;
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memset(mvif, 0, sizeof(*mvif));
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mvif->idx = idx;
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mvif->group_wcid.idx = MT_VIF_WCID(idx);
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mvif->group_wcid.hw_key_idx = -1;
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@ -71,6 +71,7 @@ int mt76x2_mcu_load_cr(struct mt76x02_dev *dev, u8 type, u8 temp_level,
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void mt76x2_cleanup(struct mt76x02_dev *dev);
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int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard);
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void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable);
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void mt76x2_init_txpower(struct mt76x02_dev *dev,
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struct ieee80211_supported_band *sband);
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@ -77,7 +77,7 @@ mt76x2_fixup_xtal(struct mt76x02_dev *dev)
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}
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}
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static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
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int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
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{
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const u8 *macaddr = dev->mt76.macaddr;
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u32 val;
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@ -165,9 +165,30 @@ mt76pci_load_firmware(struct mt76x02_dev *dev)
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return -ENOENT;
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}
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static int
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mt76pci_mcu_restart(struct mt76_dev *mdev)
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{
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struct mt76x02_dev *dev;
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int ret;
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dev = container_of(mdev, struct mt76x02_dev, mt76);
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mt76x02_mcu_cleanup(dev);
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mt76x2_mac_reset(dev, true);
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ret = mt76pci_load_firmware(dev);
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if (ret)
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return ret;
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mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
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return 0;
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}
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int mt76x2_mcu_init(struct mt76x02_dev *dev)
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{
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static const struct mt76_mcu_ops mt76x2_mcu_ops = {
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.mcu_restart = mt76pci_mcu_restart,
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.mcu_send_msg = mt76x02_mcu_msg_send,
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};
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int ret;
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@ -580,6 +580,9 @@ void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq)
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struct mt76_txq *mtxq = (struct mt76_txq *) txq->drv_priv;
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struct mt76_queue *hwq = mtxq->hwq;
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if (!test_bit(MT76_STATE_RUNNING, &dev->state))
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return;
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spin_lock_bh(&hwq->lock);
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if (list_empty(&mtxq->list))
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list_add_tail(&mtxq->list, &hwq->swq);
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