mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 06:26:39 +07:00
ARM: dts: sh73a0: Remove unnecessary clock-output-names properties
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
The clock-output-names property is left in place for the zb_clk which is
thus treated as a special case as the MSTP clock driver (clk-mstp.c)
explicitly looks for a clock with node name zb_clk for the r8a73a4 and
sh73a0 SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman
parent
57c75d1ed6
commit
000025cfbb
@ -602,39 +602,33 @@ clocks {
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ranges;
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/* External root clocks */
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extalr_clk: extalr_clk {
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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extal1_clk: extal1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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extal2_clk: extal2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extal2";
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};
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extcki_clk: extcki_clk {
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extcki_clk: extcki {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "extcki";
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};
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fsiack_clk: fsiack_clk {
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fsiack_clk: fsiack {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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fsibck_clk: fsibck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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@ -650,7 +644,7 @@ cpg_clocks: cpg_clocks@e6150000 {
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};
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/* Variable factor clocks (DIV6) */
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vclk1_clk: vclk1_clk@e6150008 {
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vclk1_clk: vclk1@e6150008 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150008 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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@ -658,9 +652,8 @@ vclk1_clk: vclk1_clk@e6150008 {
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<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
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<0>;
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#clock-cells = <0>;
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clock-output-names = "vclk1";
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};
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vclk2_clk: vclk2_clk@e615000c {
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vclk2_clk: vclk2@e615000c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615000c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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@ -668,9 +661,8 @@ vclk2_clk: vclk2_clk@e615000c {
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<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
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<0>;
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#clock-cells = <0>;
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clock-output-names = "vclk2";
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};
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vclk3_clk: vclk3_clk@e615001c {
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vclk3_clk: vclk3@e615001c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615001c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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@ -678,7 +670,6 @@ vclk3_clk: vclk3_clk@e615001c {
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<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
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<0>;
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#clock-cells = <0>;
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clock-output-names = "vclk3";
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};
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zb_clk: zb_clk@e6150010 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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@ -688,168 +679,148 @@ zb_clk: zb_clk@e6150010 {
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#clock-cells = <0>;
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clock-output-names = "zb";
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};
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flctl_clk: flctl_clk@e6150014 {
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flctl_clk: flctlck@e6150014 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150014 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
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#clock-cells = <0>;
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clock-output-names = "flctlck";
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};
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sdhi0_clk: sdhi0_clk@e6150074 {
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sdhi0_clk: sdhi0ck@e6150074 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150074 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&pll1_div13_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "sdhi0ck";
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};
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sdhi1_clk: sdhi1_clk@e6150078 {
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sdhi1_clk: sdhi1ck@e6150078 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150078 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&pll1_div13_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "sdhi1ck";
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};
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sdhi2_clk: sdhi2_clk@e615007c {
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sdhi2_clk: sdhi2ck@e615007c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615007c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&pll1_div13_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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fsia_clk: fsia_clk@e6150018 {
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fsia_clk: fsia@e6150018 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150018 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&fsiack_clk>, <&fsiack_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsia";
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};
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fsib_clk: fsib_clk@e6150090 {
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fsib_clk: fsib@e6150090 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150090 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&fsibck_clk>, <&fsibck_clk>;
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#clock-cells = <0>;
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clock-output-names = "fsib";
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};
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sub_clk: sub_clk@e6150080 {
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sub_clk: sub@e6150080 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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spua_clk: spua_clk@e6150084 {
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spua_clk: spua@e6150084 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150084 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spua";
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};
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spuv_clk: spuv_clk@e6150094 {
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spuv_clk: spuv@e6150094 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150094 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&extal2_clk>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "spuv";
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};
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msu_clk: msu_clk@e6150088 {
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msu_clk: msu@e6150088 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150088 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
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#clock-cells = <0>;
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clock-output-names = "msu";
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};
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hsi_clk: hsi_clk@e615008c {
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hsi_clk: hsi@e615008c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615008c 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&pll1_div7_clk>, <0>;
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#clock-cells = <0>;
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clock-output-names = "hsi";
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};
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mfg1_clk: mfg1_clk@e6150098 {
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mfg1_clk: mfg1@e6150098 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150098 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
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#clock-cells = <0>;
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clock-output-names = "mfg1";
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};
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mfg2_clk: mfg2_clk@e615009c {
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mfg2_clk: mfg2@e615009c {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe615009c 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
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#clock-cells = <0>;
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clock-output-names = "mfg2";
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};
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dsit_clk: dsit_clk@e6150060 {
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dsit_clk: dsit@e6150060 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150060 4>;
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clocks = <&pll1_div2_clk>, <0>,
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<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
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#clock-cells = <0>;
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clock-output-names = "dsit";
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};
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dsi0p_clk: dsi0p_clk@e6150064 {
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dsi0p_clk: dsi0pck@e6150064 {
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compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150064 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
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<&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
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<&extcki_clk>, <0>, <0>, <0>;
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#clock-cells = <0>;
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clock-output-names = "dsi0pck";
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};
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/* Fixed factor clocks */
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main_div2_clk: main_div2_clk {
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main_div2_clk: main_div2 {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "main_div2";
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};
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pll1_div2_clk: pll1_div2_clk {
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pll1_div2_clk: pll1_div2 {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pll1_div2";
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};
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pll1_div7_clk: pll1_div7_clk {
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pll1_div7_clk: pll1_div7 {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <7>;
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clock-mult = <1>;
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clock-output-names = "pll1_div7";
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};
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pll1_div13_clk: pll1_div13_clk {
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pll1_div13_clk: pll1_div13 {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <13>;
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clock-mult = <1>;
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clock-output-names = "pll1_div13";
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};
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twd_clk: twd_clk {
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twd_clk: twd {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks SH73A0_CLK_Z>;
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#clock-cells = <0>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "twd";
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};
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/* Gate clocks */
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