2014-02-19 04:46:16 +07:00
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#include <versatile-ab.dts>
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2011-07-26 16:19:06 +07:00
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/ {
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model = "ARM Versatile PB";
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compatible = "arm,versatile-pb";
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amba {
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gpio2: gpio@101e6000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e6000 0x1000>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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2014-03-02 11:22:53 +07:00
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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2011-07-26 16:19:06 +07:00
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};
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gpio3: gpio@101e7000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e7000 0x1000>;
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interrupts = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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2014-03-02 11:22:53 +07:00
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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2011-07-26 16:19:06 +07:00
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};
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fpga {
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uart@9000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x9000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <6>;
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2014-03-02 11:22:53 +07:00
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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2011-07-26 16:19:06 +07:00
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};
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sci@a000 {
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compatible = "arm,primecell";
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reg = <0xa000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <5>;
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2014-03-02 11:22:53 +07:00
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clocks = <&xtal24mhz>;
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clock-names = "apb_pclk";
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2011-07-26 16:19:06 +07:00
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};
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mmc@b000 {
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2014-03-03 15:28:38 +07:00
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compatible = "arm,pl180", "arm,primecell";
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2011-07-26 16:19:06 +07:00
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reg = <0xb000 0x1000>;
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2013-10-29 06:50:11 +07:00
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interrupts-extended = <&vic 23 &sic 2>;
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2014-03-02 11:22:53 +07:00
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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2011-07-26 16:19:06 +07:00
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};
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};
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};
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};
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