2008-04-25 01:55:23 +07:00
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/******************************************************************************
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*
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* Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/netdevice.h>
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#include <linux/wireless.h>
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#include <net/mac80211.h>
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#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "iwl-eeprom.h"
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#include "iwl-4965.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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#include "iwl-5000-hw.h"
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#define IWL5000_UCODE_API "-1"
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2008-04-25 01:55:25 +07:00
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static int iwl5000_apm_init(struct iwl_priv *priv)
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{
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int ret = 0;
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iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
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/* set "initialization complete" bit to move adapter
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* D0U* --> D0A* state */
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iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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/* wait for clock stabilization */
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ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
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CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
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if (ret < 0) {
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IWL_DEBUG_INFO("Failed to init the card\n");
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return ret;
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}
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ret = iwl_grab_nic_access(priv);
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if (ret)
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return ret;
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/* enable DMA */
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iwl_write_prph(priv, APMG_CLK_EN_REG,
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APMG_CLK_VAL_DMA_CLK_RQT);
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udelay(20);
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iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
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APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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iwl_release_nic_access(priv);
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return ret;
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}
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2008-04-25 01:55:27 +07:00
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/*
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* EEPROM
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*/
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static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
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{
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u16 offset = 0;
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if ((address & INDIRECT_ADDRESS) == 0)
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return address;
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switch (address & INDIRECT_TYPE_MSK) {
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case INDIRECT_HOST:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
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break;
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case INDIRECT_GENERAL:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
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break;
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case INDIRECT_REGULATORY:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
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break;
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case INDIRECT_CALIBRATION:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
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break;
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case INDIRECT_PROCESS_ADJST:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
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break;
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case INDIRECT_OTHERS:
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offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
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break;
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default:
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IWL_ERROR("illegal indirect type: 0x%X\n",
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address & INDIRECT_TYPE_MSK);
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break;
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}
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/* translate the offset from words to byte */
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return (address & ADDRESS_MSK) + (offset << 1);
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}
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static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
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size_t offset)
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{
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u32 address = eeprom_indirect_address(priv, offset);
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BUG_ON(address >= priv->cfg->eeprom_size);
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return &priv->eeprom[address];
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}
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2008-04-25 01:55:28 +07:00
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static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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{
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if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
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(priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
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IWL_ERROR("invalid queues_num, should be between %d and %d\n",
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IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
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return -EINVAL;
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}
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2008-04-25 01:55:27 +07:00
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2008-04-25 01:55:28 +07:00
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priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
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priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
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priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
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priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
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priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
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if (priv->cfg->mod_params->amsdu_size_8K)
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priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
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else
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priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
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priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
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priv->hw_params.max_stations = IWL5000_STATION_COUNT;
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priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
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priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
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priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
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priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
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priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
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BIT(IEEE80211_BAND_5GHZ);
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switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
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case CSR_HW_REV_TYPE_5100:
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case CSR_HW_REV_TYPE_5150:
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priv->hw_params.tx_chains_num = 1;
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priv->hw_params.rx_chains_num = 2;
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/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
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priv->hw_params.valid_tx_ant = IWL_ANTENNA_MAIN;
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priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN |
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IWL_ANTENNA_AUX);
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break;
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case CSR_HW_REV_TYPE_5300:
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case CSR_HW_REV_TYPE_5350:
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priv->hw_params.tx_chains_num = 3;
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priv->hw_params.rx_chains_num = 3;
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/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
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priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN |
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IWL_ANTENNA_AUX | 0x04);
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priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN |
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IWL_ANTENNA_AUX | 0x04);
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break;
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}
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return 0;
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}
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2008-04-25 01:55:24 +07:00
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static struct iwl_hcmd_ops iwl5000_hcmd = {
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};
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static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
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};
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static struct iwl_lib_ops iwl5000_lib = {
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2008-04-25 01:55:28 +07:00
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.set_hw_params = iwl5000_hw_set_hw_params,
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2008-04-25 01:55:25 +07:00
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.apm_ops = {
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.init = iwl5000_apm_init,
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2008-04-25 01:55:26 +07:00
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.set_pwr_src = iwl4965_set_pwr_src,
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2008-04-25 01:55:25 +07:00
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},
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2008-04-25 01:55:24 +07:00
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.eeprom_ops = {
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2008-04-25 01:55:27 +07:00
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.regulatory_bands = {
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EEPROM_5000_REG_BAND_1_CHANNELS,
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EEPROM_5000_REG_BAND_2_CHANNELS,
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EEPROM_5000_REG_BAND_3_CHANNELS,
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EEPROM_5000_REG_BAND_4_CHANNELS,
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EEPROM_5000_REG_BAND_5_CHANNELS,
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EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
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EEPROM_5000_REG_BAND_52_FAT_CHANNELS
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},
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2008-04-25 01:55:24 +07:00
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.verify_signature = iwlcore_eeprom_verify_signature,
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.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
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.release_semaphore = iwlcore_eeprom_release_semaphore,
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2008-04-25 01:55:27 +07:00
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.query_addr = iwl5000_eeprom_query_addr,
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2008-04-25 01:55:24 +07:00
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},
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};
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static struct iwl_ops iwl5000_ops = {
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.lib = &iwl5000_lib,
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.hcmd = &iwl5000_hcmd,
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.utils = &iwl5000_hcmd_utils,
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};
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2008-04-25 01:55:23 +07:00
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static struct iwl_mod_params iwl50_mod_params = {
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.num_of_queues = IWL50_NUM_QUEUES,
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.enable_qos = 1,
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.amsdu_size_8K = 1,
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/* the rest are 0 by default */
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};
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struct iwl_cfg iwl5300_agn_cfg = {
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.name = "5300AGN",
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.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
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.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
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2008-04-25 01:55:24 +07:00
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.ops = &iwl5000_ops,
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2008-04-25 01:55:27 +07:00
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.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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2008-04-25 01:55:23 +07:00
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.mod_params = &iwl50_mod_params,
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};
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struct iwl_cfg iwl5100_agn_cfg = {
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.name = "5100AGN",
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.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
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.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
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2008-04-25 01:55:24 +07:00
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.ops = &iwl5000_ops,
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2008-04-25 01:55:27 +07:00
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.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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2008-04-25 01:55:23 +07:00
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.mod_params = &iwl50_mod_params,
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};
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struct iwl_cfg iwl5350_agn_cfg = {
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.name = "5350AGN",
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.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
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.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
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2008-04-25 01:55:24 +07:00
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.ops = &iwl5000_ops,
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2008-04-25 01:55:27 +07:00
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.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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2008-04-25 01:55:23 +07:00
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.mod_params = &iwl50_mod_params,
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};
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module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
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MODULE_PARM_DESC(disable50,
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"manually disable the 50XX radio (default 0 [radio on])");
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module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
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MODULE_PARM_DESC(swcrypto50,
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"using software crypto engine (default 0 [hardware])\n");
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module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
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MODULE_PARM_DESC(debug50, "50XX debug output mask");
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module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
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MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
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module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
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MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
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module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
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MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
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