2012-07-26 21:01:32 +07:00
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/*
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* Device Tree Source for OMAP2420 SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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2013-05-31 19:32:55 +07:00
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#include "omap2.dtsi"
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2012-07-26 21:01:32 +07:00
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/ {
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compatible = "ti,omap2420", "ti,omap2";
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ocp {
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2015-02-12 15:38:16 +07:00
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l4: l4@48000000 {
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compatible = "ti,omap2-l4", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x48000000 0x100000>;
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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prcm: prcm@8000 {
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compatible = "ti,omap2-prcm";
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reg = <0x8000 0x1000>;
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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prcm_clockdomains: clockdomains {
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};
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};
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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scm: scm@0 {
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compatible = "ti,omap2-scm", "simple-bus";
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reg = <0x0 0x1000>;
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2014-02-21 22:05:02 +07:00
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#address-cells = <1>;
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2015-02-12 15:38:16 +07:00
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#size-cells = <1>;
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2016-11-07 22:27:49 +07:00
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#pinctrl-cells = <1>;
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2015-02-12 15:38:16 +07:00
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ranges = <0 0x0 0x1000>;
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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omap2420_pmx: pinmux@30 {
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compatible = "ti,omap2420-padconf",
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"pinctrl-single";
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reg = <0x30 0x0113>;
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#address-cells = <1>;
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#size-cells = <0>;
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2016-11-07 22:27:49 +07:00
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#pinctrl-cells = <1>;
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2015-02-12 15:38:16 +07:00
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pinctrl-single,register-width = <8>;
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pinctrl-single,function-mask = <0x3f>;
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};
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2014-02-21 22:05:02 +07:00
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2015-02-12 15:38:16 +07:00
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scm_conf: scm_conf@270 {
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compatible = "syscon";
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reg = <0x270 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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2012-10-26 02:24:14 +07:00
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2015-02-12 15:38:16 +07:00
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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scm_clockdomains: clockdomains {
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};
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};
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counter32k: counter@4000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4000 0x20>;
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ti,hwmods = "counter_32k";
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};
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2012-09-11 00:34:51 +07:00
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};
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2013-03-01 04:32:00 +07:00
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gpio1: gpio@48018000 {
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compatible = "ti,omap2-gpio";
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reg = <0x48018000 0x200>;
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interrupts = <29>;
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ti,hwmods = "gpio1";
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2013-04-05 03:16:16 +07:00
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ti,gpio-always-on;
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2013-03-01 04:32:00 +07:00
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio2: gpio@4801a000 {
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compatible = "ti,omap2-gpio";
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reg = <0x4801a000 0x200>;
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interrupts = <30>;
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ti,hwmods = "gpio2";
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2013-04-05 03:16:16 +07:00
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ti,gpio-always-on;
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2013-03-01 04:32:00 +07:00
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio3: gpio@4801c000 {
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compatible = "ti,omap2-gpio";
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reg = <0x4801c000 0x200>;
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interrupts = <31>;
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ti,hwmods = "gpio3";
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2013-04-05 03:16:16 +07:00
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ti,gpio-always-on;
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2013-03-01 04:32:00 +07:00
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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gpio4: gpio@4801e000 {
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compatible = "ti,omap2-gpio";
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reg = <0x4801e000 0x200>;
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interrupts = <32>;
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ti,hwmods = "gpio4";
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2013-04-05 03:16:16 +07:00
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ti,gpio-always-on;
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2013-03-01 04:32:00 +07:00
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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2013-02-23 04:33:31 +07:00
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gpmc: gpmc@6800a000 {
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compatible = "ti,omap2420-gpmc";
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reg = <0x6800a000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <20>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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2016-04-07 17:25:28 +07:00
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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2013-02-23 04:33:31 +07:00
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};
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2012-07-26 21:01:32 +07:00
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mcbsp1: mcbsp@48074000 {
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compatible = "ti,omap2420-mcbsp";
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reg = <0x48074000 0xff>;
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reg-names = "mpu";
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interrupts = <59>, /* TX interrupt */
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<60>; /* RX interrupt */
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interrupt-names = "tx", "rx";
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ti,hwmods = "mcbsp1";
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2013-03-11 14:50:21 +07:00
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dmas = <&sdma 31>,
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<&sdma 32>;
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dma-names = "tx", "rx";
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2014-01-24 15:19:06 +07:00
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status = "disabled";
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2012-07-26 21:01:32 +07:00
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};
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mcbsp2: mcbsp@48076000 {
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compatible = "ti,omap2420-mcbsp";
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reg = <0x48076000 0xff>;
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reg-names = "mpu";
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interrupts = <62>, /* TX interrupt */
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<63>; /* RX interrupt */
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interrupt-names = "tx", "rx";
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ti,hwmods = "mcbsp2";
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2013-03-11 14:50:21 +07:00
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dmas = <&sdma 33>,
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<&sdma 34>;
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dma-names = "tx", "rx";
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2014-01-24 15:19:06 +07:00
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status = "disabled";
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2012-07-26 21:01:32 +07:00
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};
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2012-10-19 21:59:00 +07:00
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2013-11-15 06:25:09 +07:00
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msdi1: mmc@4809c000 {
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compatible = "ti,omap2420-mmc";
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ti,hwmods = "msdi1";
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reg = <0x4809c000 0x80>;
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interrupts = <83>;
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dmas = <&sdma 61 &sdma 62>;
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dma-names = "tx", "rx";
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};
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2014-04-23 05:23:36 +07:00
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mailbox: mailbox@48094000 {
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compatible = "ti,omap2-mailbox";
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reg = <0x48094000 0x200>;
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interrupts = <26>, <34>;
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interrupt-names = "dsp", "iva";
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ti,hwmods = "mailbox";
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2014-11-04 06:07:35 +07:00
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#mbox-cells = <1>;
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2014-07-12 04:44:34 +07:00
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <6>;
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2014-09-11 02:27:23 +07:00
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mbox_dsp: dsp {
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <1 0 0>;
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};
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mbox_iva: iva {
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ti,mbox-tx = <2 1 3>;
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ti,mbox-rx = <3 1 3>;
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};
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2014-04-23 05:23:36 +07:00
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};
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2012-10-19 21:59:00 +07:00
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timer1: timer@48028000 {
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2013-03-20 00:38:18 +07:00
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compatible = "ti,omap2420-timer";
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2012-10-19 21:59:00 +07:00
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reg = <0x48028000 0x400>;
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interrupts = <37>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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};
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2013-11-15 06:25:09 +07:00
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wd_timer2: wdt@48022000 {
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compatible = "ti,omap2-wdt";
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ti,hwmods = "wd_timer2";
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reg = <0x48022000 0x80>;
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};
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2012-07-26 21:01:32 +07:00
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};
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};
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2013-11-15 06:25:09 +07:00
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&i2c1 {
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compatible = "ti,omap2420-i2c";
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};
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&i2c2 {
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compatible = "ti,omap2420-i2c";
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};
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2014-02-24 23:51:05 +07:00
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/include/ "omap24xx-clocks.dtsi"
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/include/ "omap2420-clocks.dtsi"
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