2005-04-17 05:20:36 +07:00
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#ifndef __ASM_CPU_SH3_DMA_H
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#define __ASM_CPU_SH3_DMA_H
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2007-12-26 09:45:06 +07:00
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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2009-03-10 15:26:49 +07:00
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7712)
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#define SH_DMAC_BASE0 0xa4010020
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#else /* SH7705/06/07/09 */
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#define SH_DMAC_BASE0 0xa4000020
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2008-05-06 17:36:27 +07:00
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#endif
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2007-08-20 06:59:33 +07:00
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#define DMTE0_IRQ 48
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#define DMTE4_IRQ 76
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2005-04-17 05:20:36 +07:00
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2006-01-17 13:14:09 +07:00
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/* Definitions for the SuperH DMAC */
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#define TM_BURST 0x00000020
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#define TS_8 0x00000000
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#define TS_16 0x00000008
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#define TS_32 0x00000010
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#define TS_128 0x00000018
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#endif /* __ASM_CPU_SH3_DMA_H */
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