2018-08-23 20:34:54 +07:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2009-09-07 10:26:23 +07:00
|
|
|
/*
|
|
|
|
* Renesas SuperH DMA Engine support
|
|
|
|
*
|
|
|
|
* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
|
|
|
|
* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
#ifndef __DMA_SHDMA_H
|
|
|
|
#define __DMA_SHDMA_H
|
|
|
|
|
2012-07-05 17:29:40 +07:00
|
|
|
#include <linux/sh_dma.h>
|
2012-05-09 22:09:21 +07:00
|
|
|
#include <linux/shdma-base.h>
|
2009-09-07 10:26:23 +07:00
|
|
|
#include <linux/dmaengine.h>
|
2009-12-17 23:41:39 +07:00
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/list.h>
|
2009-09-07 10:26:23 +07:00
|
|
|
|
2012-05-09 22:09:21 +07:00
|
|
|
#define SH_DMAE_MAX_CHANNELS 20
|
|
|
|
#define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */
|
2009-09-07 10:26:23 +07:00
|
|
|
|
2009-12-17 23:41:39 +07:00
|
|
|
struct device;
|
|
|
|
|
2009-09-07 10:26:23 +07:00
|
|
|
struct sh_dmae_chan {
|
2012-05-09 22:09:21 +07:00
|
|
|
struct shdma_chan shdma_chan;
|
2012-07-05 17:29:40 +07:00
|
|
|
const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
|
2010-02-03 21:46:41 +07:00
|
|
|
int xmit_shift; /* log_2(bytes_per_xfer) */
|
2013-07-02 22:46:01 +07:00
|
|
|
void __iomem *base;
|
2009-12-11 00:35:07 +07:00
|
|
|
char dev_id[16]; /* unique name per DMAC of channel */
|
2011-04-30 00:09:25 +07:00
|
|
|
int pm_error;
|
2013-08-02 21:50:36 +07:00
|
|
|
dma_addr_t slave_addr;
|
2009-09-07 10:26:23 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct sh_dmae_device {
|
2012-05-09 22:09:21 +07:00
|
|
|
struct shdma_dev shdma_dev;
|
|
|
|
struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
|
2013-08-02 21:18:09 +07:00
|
|
|
const struct sh_dmae_pdata *pdata;
|
2010-12-17 17:16:10 +07:00
|
|
|
struct list_head node;
|
2013-07-02 22:46:01 +07:00
|
|
|
void __iomem *chan_reg;
|
|
|
|
void __iomem *dmars;
|
2011-06-17 15:20:40 +07:00
|
|
|
unsigned int chcr_offset;
|
2011-06-17 15:20:51 +07:00
|
|
|
u32 chcr_ie_bit;
|
2009-09-07 10:26:23 +07:00
|
|
|
};
|
|
|
|
|
2012-05-09 22:09:21 +07:00
|
|
|
struct sh_dmae_regs {
|
|
|
|
u32 sar; /* SAR / source address */
|
|
|
|
u32 dar; /* DAR / destination address */
|
|
|
|
u32 tcr; /* TCR / transfer count */
|
|
|
|
};
|
|
|
|
|
|
|
|
struct sh_dmae_desc {
|
|
|
|
struct sh_dmae_regs hw;
|
|
|
|
struct shdma_desc shdma_desc;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
|
2009-09-07 10:26:23 +07:00
|
|
|
#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
|
|
|
|
#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
|
2012-05-09 22:09:21 +07:00
|
|
|
#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
|
|
|
|
struct sh_dmae_device, shdma_dev.dma_dev)
|
2009-09-07 10:26:23 +07:00
|
|
|
|
|
|
|
#endif /* __DMA_SHDMA_H */
|