2019-05-27 13:55:08 +07:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2012-05-09 21:59:01 +07:00
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#include <linux/export.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <video/imx-ipu-v3.h>
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#include "ipu-prv.h"
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc {
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struct ipu_smfc_priv *priv;
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int chno;
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bool inuse;
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};
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2012-05-09 21:59:01 +07:00
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struct ipu_smfc_priv {
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void __iomem *base;
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spinlock_t lock;
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2014-06-26 08:05:34 +07:00
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struct ipu_soc *ipu;
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struct ipu_smfc channel[4];
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int use_count;
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2012-05-09 21:59:01 +07:00
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};
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/*SMFC Registers */
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#define SMFC_MAP 0x0000
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#define SMFC_WMC 0x0004
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#define SMFC_BS 0x0008
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2014-06-26 08:05:34 +07:00
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int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize)
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2012-05-09 21:59:01 +07:00
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{
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc_priv *priv = smfc->priv;
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2012-05-09 21:59:01 +07:00
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unsigned long flags;
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u32 val, shift;
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2014-06-26 08:05:34 +07:00
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spin_lock_irqsave(&priv->lock, flags);
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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shift = smfc->chno * 4;
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val = readl(priv->base + SMFC_BS);
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2012-05-09 21:59:01 +07:00
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val &= ~(0xf << shift);
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val |= burstsize << shift;
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2014-06-26 08:05:34 +07:00
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writel(val, priv->base + SMFC_BS);
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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spin_unlock_irqrestore(&priv->lock, flags);
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2012-05-09 21:59:01 +07:00
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_set_burstsize);
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2014-06-26 08:05:34 +07:00
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int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id)
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2012-05-09 21:59:01 +07:00
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{
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc_priv *priv = smfc->priv;
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2012-05-09 21:59:01 +07:00
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unsigned long flags;
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u32 val, shift;
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2014-06-26 08:05:34 +07:00
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spin_lock_irqsave(&priv->lock, flags);
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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shift = smfc->chno * 3;
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val = readl(priv->base + SMFC_MAP);
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2012-05-09 21:59:01 +07:00
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val &= ~(0x7 << shift);
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val |= ((csi_id << 2) | mipi_id) << shift;
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2014-06-26 08:05:34 +07:00
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writel(val, priv->base + SMFC_MAP);
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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spin_unlock_irqrestore(&priv->lock, flags);
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2012-05-09 21:59:01 +07:00
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_map_channel);
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2014-06-26 08:05:35 +07:00
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int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level)
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{
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struct ipu_smfc_priv *priv = smfc->priv;
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unsigned long flags;
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u32 val, shift;
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spin_lock_irqsave(&priv->lock, flags);
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shift = smfc->chno * 6 + (smfc->chno > 1 ? 4 : 0);
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val = readl(priv->base + SMFC_WMC);
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val &= ~(0x3f << shift);
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val |= ((clr_level << 3) | set_level) << shift;
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writel(val, priv->base + SMFC_WMC);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_set_watermark);
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2014-06-26 08:05:34 +07:00
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int ipu_smfc_enable(struct ipu_smfc *smfc)
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2014-06-26 08:05:33 +07:00
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{
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc_priv *priv = smfc->priv;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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if (!priv->use_count)
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ipu_module_enable(priv->ipu, IPU_CONF_SMFC_EN);
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priv->use_count++;
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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2014-06-26 08:05:33 +07:00
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_enable);
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2014-06-26 08:05:34 +07:00
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int ipu_smfc_disable(struct ipu_smfc *smfc)
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2014-06-26 08:05:33 +07:00
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{
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc_priv *priv = smfc->priv;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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priv->use_count--;
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if (!priv->use_count)
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ipu_module_disable(priv->ipu, IPU_CONF_SMFC_EN);
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if (priv->use_count < 0)
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priv->use_count = 0;
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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2014-06-26 08:05:33 +07:00
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_disable);
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno)
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{
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struct ipu_smfc_priv *priv = ipu->smfc_priv;
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struct ipu_smfc *smfc, *ret;
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unsigned long flags;
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if (chno >= 4)
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return ERR_PTR(-EINVAL);
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smfc = &priv->channel[chno];
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ret = smfc;
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spin_lock_irqsave(&priv->lock, flags);
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if (smfc->inuse) {
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ret = ERR_PTR(-EBUSY);
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goto unlock;
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}
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smfc->inuse = true;
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unlock:
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spin_unlock_irqrestore(&priv->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_get);
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void ipu_smfc_put(struct ipu_smfc *smfc)
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{
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struct ipu_smfc_priv *priv = smfc->priv;
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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smfc->inuse = false;
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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EXPORT_SYMBOL_GPL(ipu_smfc_put);
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2012-05-09 21:59:01 +07:00
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int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev,
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unsigned long base)
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{
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2014-06-26 08:05:34 +07:00
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struct ipu_smfc_priv *priv;
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int i;
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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2012-05-09 21:59:01 +07:00
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return -ENOMEM;
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2014-06-26 08:05:34 +07:00
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ipu->smfc_priv = priv;
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spin_lock_init(&priv->lock);
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priv->ipu = ipu;
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2012-05-09 21:59:01 +07:00
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2014-06-26 08:05:34 +07:00
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priv->base = devm_ioremap(dev, base, PAGE_SIZE);
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if (!priv->base)
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2012-05-09 21:59:01 +07:00
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return -ENOMEM;
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2014-06-26 08:05:34 +07:00
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for (i = 0; i < 4; i++) {
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priv->channel[i].priv = priv;
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priv->channel[i].chno = i;
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}
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pr_debug("%s: ioremap 0x%08lx -> %p\n", __func__, base, priv->base);
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2012-05-09 21:59:01 +07:00
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return 0;
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}
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void ipu_smfc_exit(struct ipu_soc *ipu)
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{
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}
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