2006-04-03 01:21:26 +07:00
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/*
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* NetChip 2280 high/full speed USB device controller.
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* Unlike many such controllers, this one talks PCI.
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*/
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#ifndef __LINUX_USB_NET2280_H
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#define __LINUX_USB_NET2280_H
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/*
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* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
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* Copyright (C) 2003 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*-------------------------------------------------------------------------*/
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/* NET2280 MEMORY MAPPED REGISTERS
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*
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* The register layout came from the chip documentation, and the bit
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* number definitions were extracted from chip specification.
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*
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* Use the shift operator ('<<') to build bit masks, with readl/writel
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* to access the registers through PCI.
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*/
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/* main registers, BAR0 + 0x0000 */
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struct net2280_regs {
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2008-01-31 06:21:33 +07:00
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/* offset 0x0000 */
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2006-04-03 01:21:26 +07:00
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u32 devinit;
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#define LOCAL_CLOCK_FREQUENCY 8
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#define FORCE_PCI_RESET 7
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#define PCI_ID 6
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#define PCI_ENABLE 5
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#define FIFO_SOFT_RESET 4
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#define CFG_SOFT_RESET 3
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#define PCI_SOFT_RESET 2
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#define USB_SOFT_RESET 1
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#define M8051_RESET 0
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u32 eectl;
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#define EEPROM_ADDRESS_WIDTH 23
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#define EEPROM_CHIP_SELECT_ACTIVE 22
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#define EEPROM_PRESENT 21
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#define EEPROM_VALID 20
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#define EEPROM_BUSY 19
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#define EEPROM_CHIP_SELECT_ENABLE 18
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#define EEPROM_BYTE_READ_START 17
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#define EEPROM_BYTE_WRITE_START 16
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#define EEPROM_READ_DATA 8
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#define EEPROM_WRITE_DATA 0
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u32 eeclkfreq;
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u32 _unused0;
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2008-01-31 06:21:33 +07:00
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/* offset 0x0010 */
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2006-04-03 01:21:26 +07:00
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u32 pciirqenb0; /* interrupt PCI master ... */
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#define SETUP_PACKET_INTERRUPT_ENABLE 7
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#define ENDPOINT_F_INTERRUPT_ENABLE 6
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#define ENDPOINT_E_INTERRUPT_ENABLE 5
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#define ENDPOINT_D_INTERRUPT_ENABLE 4
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#define ENDPOINT_C_INTERRUPT_ENABLE 3
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#define ENDPOINT_B_INTERRUPT_ENABLE 2
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#define ENDPOINT_A_INTERRUPT_ENABLE 1
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#define ENDPOINT_0_INTERRUPT_ENABLE 0
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u32 pciirqenb1;
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#define PCI_INTERRUPT_ENABLE 31
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#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
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#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
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#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
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#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
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#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
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#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18
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#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
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#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
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#define GPIO_INTERRUPT_ENABLE 13
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#define DMA_D_INTERRUPT_ENABLE 12
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#define DMA_C_INTERRUPT_ENABLE 11
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#define DMA_B_INTERRUPT_ENABLE 10
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#define DMA_A_INTERRUPT_ENABLE 9
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#define EEPROM_DONE_INTERRUPT_ENABLE 8
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#define VBUS_INTERRUPT_ENABLE 7
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#define CONTROL_STATUS_INTERRUPT_ENABLE 6
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#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
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#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
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#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
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#define RESUME_INTERRUPT_ENABLE 1
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#define SOF_INTERRUPT_ENABLE 0
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u32 cpu_irqenb0; /* ... or onboard 8051 */
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#define SETUP_PACKET_INTERRUPT_ENABLE 7
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#define ENDPOINT_F_INTERRUPT_ENABLE 6
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#define ENDPOINT_E_INTERRUPT_ENABLE 5
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#define ENDPOINT_D_INTERRUPT_ENABLE 4
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#define ENDPOINT_C_INTERRUPT_ENABLE 3
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#define ENDPOINT_B_INTERRUPT_ENABLE 2
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#define ENDPOINT_A_INTERRUPT_ENABLE 1
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#define ENDPOINT_0_INTERRUPT_ENABLE 0
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u32 cpu_irqenb1;
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#define CPU_INTERRUPT_ENABLE 31
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#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
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#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
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#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
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#define PCI_INTA_INTERRUPT_ENABLE 24
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#define PCI_PME_INTERRUPT_ENABLE 23
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#define PCI_SERR_INTERRUPT_ENABLE 22
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#define PCI_PERR_INTERRUPT_ENABLE 21
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#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
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#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
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#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
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#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
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#define GPIO_INTERRUPT_ENABLE 13
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#define DMA_D_INTERRUPT_ENABLE 12
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#define DMA_C_INTERRUPT_ENABLE 11
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#define DMA_B_INTERRUPT_ENABLE 10
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#define DMA_A_INTERRUPT_ENABLE 9
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#define EEPROM_DONE_INTERRUPT_ENABLE 8
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#define VBUS_INTERRUPT_ENABLE 7
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#define CONTROL_STATUS_INTERRUPT_ENABLE 6
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#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
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#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
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#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
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#define RESUME_INTERRUPT_ENABLE 1
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#define SOF_INTERRUPT_ENABLE 0
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2008-01-31 06:21:33 +07:00
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/* offset 0x0020 */
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2006-04-03 01:21:26 +07:00
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u32 _unused1;
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u32 usbirqenb1;
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#define USB_INTERRUPT_ENABLE 31
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#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
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#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
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#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
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#define PCI_INTA_INTERRUPT_ENABLE 24
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#define PCI_PME_INTERRUPT_ENABLE 23
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#define PCI_SERR_INTERRUPT_ENABLE 22
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#define PCI_PERR_INTERRUPT_ENABLE 21
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#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
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#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
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#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
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#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
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#define GPIO_INTERRUPT_ENABLE 13
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#define DMA_D_INTERRUPT_ENABLE 12
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#define DMA_C_INTERRUPT_ENABLE 11
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#define DMA_B_INTERRUPT_ENABLE 10
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#define DMA_A_INTERRUPT_ENABLE 9
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#define EEPROM_DONE_INTERRUPT_ENABLE 8
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#define VBUS_INTERRUPT_ENABLE 7
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#define CONTROL_STATUS_INTERRUPT_ENABLE 6
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#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
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#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
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#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
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#define RESUME_INTERRUPT_ENABLE 1
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#define SOF_INTERRUPT_ENABLE 0
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u32 irqstat0;
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#define INTA_ASSERTED 12
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#define SETUP_PACKET_INTERRUPT 7
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#define ENDPOINT_F_INTERRUPT 6
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#define ENDPOINT_E_INTERRUPT 5
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#define ENDPOINT_D_INTERRUPT 4
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#define ENDPOINT_C_INTERRUPT 3
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#define ENDPOINT_B_INTERRUPT 2
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#define ENDPOINT_A_INTERRUPT 1
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#define ENDPOINT_0_INTERRUPT 0
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u32 irqstat1;
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#define POWER_STATE_CHANGE_INTERRUPT 27
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#define PCI_ARBITER_TIMEOUT_INTERRUPT 26
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#define PCI_PARITY_ERROR_INTERRUPT 25
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#define PCI_INTA_INTERRUPT 24
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#define PCI_PME_INTERRUPT 23
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#define PCI_SERR_INTERRUPT 22
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#define PCI_PERR_INTERRUPT 21
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#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20
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#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19
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#define PCI_RETRY_ABORT_INTERRUPT 17
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#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16
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#define SOF_DOWN_INTERRUPT 14
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#define GPIO_INTERRUPT 13
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#define DMA_D_INTERRUPT 12
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#define DMA_C_INTERRUPT 11
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#define DMA_B_INTERRUPT 10
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#define DMA_A_INTERRUPT 9
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#define EEPROM_DONE_INTERRUPT 8
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#define VBUS_INTERRUPT 7
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#define CONTROL_STATUS_INTERRUPT 6
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#define ROOT_PORT_RESET_INTERRUPT 4
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#define SUSPEND_REQUEST_INTERRUPT 3
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#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2
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#define RESUME_INTERRUPT 1
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#define SOF_INTERRUPT 0
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2008-01-31 06:21:33 +07:00
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/* offset 0x0030 */
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2006-04-03 01:21:26 +07:00
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u32 idxaddr;
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u32 idxdata;
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u32 fifoctl;
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#define PCI_BASE2_RANGE 16
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#define IGNORE_FIFO_AVAILABILITY 3
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#define PCI_BASE2_SELECT 2
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#define FIFO_CONFIGURATION_SELECT 0
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u32 _unused2;
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2008-01-31 06:21:33 +07:00
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/* offset 0x0040 */
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2006-04-03 01:21:26 +07:00
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u32 memaddr;
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#define START 28
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#define DIRECTION 27
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#define FIFO_DIAGNOSTIC_SELECT 24
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#define MEMORY_ADDRESS 0
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u32 memdata0;
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u32 memdata1;
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u32 _unused3;
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2008-01-31 06:21:33 +07:00
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/* offset 0x0050 */
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2006-04-03 01:21:26 +07:00
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u32 gpioctl;
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#define GPIO3_LED_SELECT 12
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#define GPIO3_INTERRUPT_ENABLE 11
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#define GPIO2_INTERRUPT_ENABLE 10
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#define GPIO1_INTERRUPT_ENABLE 9
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#define GPIO0_INTERRUPT_ENABLE 8
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#define GPIO3_OUTPUT_ENABLE 7
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#define GPIO2_OUTPUT_ENABLE 6
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#define GPIO1_OUTPUT_ENABLE 5
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#define GPIO0_OUTPUT_ENABLE 4
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#define GPIO3_DATA 3
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#define GPIO2_DATA 2
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#define GPIO1_DATA 1
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#define GPIO0_DATA 0
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u32 gpiostat;
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#define GPIO3_INTERRUPT 3
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#define GPIO2_INTERRUPT 2
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#define GPIO1_INTERRUPT 1
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#define GPIO0_INTERRUPT 0
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} __attribute__ ((packed));
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/* usb control, BAR0 + 0x0080 */
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struct net2280_usb_regs {
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2008-01-31 06:21:33 +07:00
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/* offset 0x0080 */
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2006-04-03 01:21:26 +07:00
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u32 stdrsp;
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#define STALL_UNSUPPORTED_REQUESTS 31
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#define SET_TEST_MODE 16
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#define GET_OTHER_SPEED_CONFIGURATION 15
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#define GET_DEVICE_QUALIFIER 14
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#define SET_ADDRESS 13
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#define ENDPOINT_SET_CLEAR_HALT 12
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#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11
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#define GET_STRING_DESCRIPTOR_2 10
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#define GET_STRING_DESCRIPTOR_1 9
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#define GET_STRING_DESCRIPTOR_0 8
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#define GET_SET_INTERFACE 6
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#define GET_SET_CONFIGURATION 5
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#define GET_CONFIGURATION_DESCRIPTOR 4
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#define GET_DEVICE_DESCRIPTOR 3
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#define GET_ENDPOINT_STATUS 2
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#define GET_INTERFACE_STATUS 1
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#define GET_DEVICE_STATUS 0
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u32 prodvendid;
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#define PRODUCT_ID 16
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#define VENDOR_ID 0
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u32 relnum;
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u32 usbctl;
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#define SERIAL_NUMBER_INDEX 16
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#define PRODUCT_ID_STRING_ENABLE 13
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#define VENDOR_ID_STRING_ENABLE 12
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#define USB_ROOT_PORT_WAKEUP_ENABLE 11
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#define VBUS_PIN 10
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#define TIMED_DISCONNECT 9
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#define SUSPEND_IMMEDIATELY 7
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#define SELF_POWERED_USB_DEVICE 6
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#define REMOTE_WAKEUP_SUPPORT 5
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#define PME_POLARITY 4
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#define USB_DETECT_ENABLE 3
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#define PME_WAKEUP_ENABLE 2
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#define DEVICE_REMOTE_WAKEUP_ENABLE 1
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#define SELF_POWERED_STATUS 0
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2008-01-31 06:21:33 +07:00
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/* offset 0x0090 */
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2006-04-03 01:21:26 +07:00
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u32 usbstat;
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#define HIGH_SPEED 7
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#define FULL_SPEED 6
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#define GENERATE_RESUME 5
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#define GENERATE_DEVICE_REMOTE_WAKEUP 4
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u32 xcvrdiag;
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#define FORCE_HIGH_SPEED_MODE 31
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#define FORCE_FULL_SPEED_MODE 30
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#define USB_TEST_MODE 24
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#define LINE_STATE 16
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#define TRANSCEIVER_OPERATION_MODE 2
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#define TRANSCEIVER_SELECT 1
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#define TERMINATION_SELECT 0
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u32 setup0123;
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u32 setup4567;
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2008-01-31 06:21:33 +07:00
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/* offset 0x0090 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 _unused0;
|
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|
|
|
u32 ouraddr;
|
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|
|
|
#define FORCE_IMMEDIATE 7
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|
|
|
|
#define OUR_USB_ADDRESS 0
|
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|
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|
u32 ourconfig;
|
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|
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|
} __attribute__ ((packed));
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|
/* pci control, BAR0 + 0x0100 */
|
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|
|
|
struct net2280_pci_regs {
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0100 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 pcimstctl;
|
|
|
|
|
#define PCI_ARBITER_PARK_SELECT 13
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|
#define PCI_MULTI LEVEL_ARBITER 12
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|
#define PCI_RETRY_ABORT_ENABLE 11
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|
#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10
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|
|
#define DMA_READ_MULTIPLE_ENABLE 9
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|
|
#define DMA_READ_LINE_ENABLE 8
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|
#define PCI_MASTER_COMMAND_SELECT 6
|
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|
|
#define MEM_READ_OR_WRITE 0
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|
#define IO_READ_OR_WRITE 1
|
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|
#define CFG_READ_OR_WRITE 2
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|
#define PCI_MASTER_START 5
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|
#define PCI_MASTER_READ_WRITE 4
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|
#define PCI_MASTER_WRITE 0
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|
#define PCI_MASTER_READ 1
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|
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|
#define PCI_MASTER_BYTE_WRITE_ENABLES 0
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|
|
u32 pcimstaddr;
|
|
|
|
|
u32 pcimstdata;
|
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|
u32 pcimststat;
|
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|
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|
#define PCI_ARBITER_CLEAR 2
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|
#define PCI_EXTERNAL_ARBITER 1
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|
#define PCI_HOST_MODE 0
|
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|
|
|
} __attribute__ ((packed));
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|
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|
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|
|
/* dma control, BAR0 + 0x0180 ... array of four structs like this,
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|
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|
* for channels 0..3. see also struct net2280_dma: descriptor
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|
* that can be loaded into some of these registers.
|
|
|
|
|
*/
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|
|
struct net2280_dma_regs { /* [11.7] */
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 dmactl;
|
|
|
|
|
#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25
|
|
|
|
|
#define DMA_CLEAR_COUNT_ENABLE 21
|
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|
|
#define DESCRIPTOR_POLLING_RATE 19
|
|
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|
|
#define POLL_CONTINUOUS 0
|
|
|
|
|
#define POLL_1_USEC 1
|
|
|
|
|
#define POLL_100_USEC 2
|
|
|
|
|
#define POLL_1_MSEC 3
|
|
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|
|
#define DMA_VALID_BIT_POLLING_ENABLE 18
|
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|
|
|
#define DMA_VALID_BIT_ENABLE 17
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|
#define DMA_SCATTER_GATHER_ENABLE 16
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|
#define DMA_OUT_AUTO_START_ENABLE 4
|
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|
|
#define DMA_PREEMPT_ENABLE 3
|
|
|
|
|
#define DMA_FIFO_VALIDATE 2
|
|
|
|
|
#define DMA_ENABLE 1
|
|
|
|
|
#define DMA_ADDRESS_HOLD 0
|
|
|
|
|
u32 dmastat;
|
|
|
|
|
#define DMA_ABORT_DONE_INTERRUPT 27
|
|
|
|
|
#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25
|
|
|
|
|
#define DMA_TRANSACTION_DONE_INTERRUPT 24
|
|
|
|
|
#define DMA_ABORT 1
|
|
|
|
|
#define DMA_START 0
|
|
|
|
|
u32 _unused0 [2];
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 dmacount;
|
|
|
|
|
#define VALID_BIT 31
|
|
|
|
|
#define DMA_DIRECTION 30
|
|
|
|
|
#define DMA_DONE_INTERRUPT_ENABLE 29
|
|
|
|
|
#define END_OF_CHAIN 28
|
|
|
|
|
#define DMA_BYTE_COUNT_MASK ((1<<24)-1)
|
|
|
|
|
#define DMA_BYTE_COUNT 0
|
|
|
|
|
u32 dmaaddr;
|
|
|
|
|
u32 dmadesc;
|
|
|
|
|
u32 _unused1;
|
|
|
|
|
} __attribute__ ((packed));
|
|
|
|
|
|
|
|
|
|
/* dedicated endpoint registers, BAR0 + 0x0200 */
|
|
|
|
|
|
|
|
|
|
struct net2280_dep_regs { /* [11.8] */
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 dep_cfg;
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 dep_rsp;
|
|
|
|
|
u32 _unused [2];
|
|
|
|
|
} __attribute__ ((packed));
|
|
|
|
|
|
|
|
|
|
/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
|
|
|
|
|
* like this, for ep0 then the configurable endpoints A..F
|
|
|
|
|
* ep0 reserved for control; E and F have only 64 bytes of fifo
|
|
|
|
|
*/
|
|
|
|
|
struct net2280_ep_regs { /* [11.9] */
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 ep_cfg;
|
|
|
|
|
#define ENDPOINT_BYTE_COUNT 16
|
|
|
|
|
#define ENDPOINT_ENABLE 10
|
|
|
|
|
#define ENDPOINT_TYPE 8
|
|
|
|
|
#define ENDPOINT_DIRECTION 7
|
|
|
|
|
#define ENDPOINT_NUMBER 0
|
|
|
|
|
u32 ep_rsp;
|
|
|
|
|
#define SET_NAK_OUT_PACKETS 15
|
|
|
|
|
#define SET_EP_HIDE_STATUS_PHASE 14
|
|
|
|
|
#define SET_EP_FORCE_CRC_ERROR 13
|
|
|
|
|
#define SET_INTERRUPT_MODE 12
|
|
|
|
|
#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11
|
|
|
|
|
#define SET_NAK_OUT_PACKETS_MODE 10
|
|
|
|
|
#define SET_ENDPOINT_TOGGLE 9
|
|
|
|
|
#define SET_ENDPOINT_HALT 8
|
|
|
|
|
#define CLEAR_NAK_OUT_PACKETS 7
|
|
|
|
|
#define CLEAR_EP_HIDE_STATUS_PHASE 6
|
|
|
|
|
#define CLEAR_EP_FORCE_CRC_ERROR 5
|
|
|
|
|
#define CLEAR_INTERRUPT_MODE 4
|
|
|
|
|
#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3
|
|
|
|
|
#define CLEAR_NAK_OUT_PACKETS_MODE 2
|
|
|
|
|
#define CLEAR_ENDPOINT_TOGGLE 1
|
|
|
|
|
#define CLEAR_ENDPOINT_HALT 0
|
|
|
|
|
u32 ep_irqenb;
|
|
|
|
|
#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6
|
|
|
|
|
#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5
|
|
|
|
|
#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
|
|
|
|
|
#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
|
|
|
|
|
#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1
|
|
|
|
|
#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
|
|
|
|
|
u32 ep_stat;
|
|
|
|
|
#define FIFO_VALID_COUNT 24
|
|
|
|
|
#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22
|
|
|
|
|
#define TIMEOUT 21
|
|
|
|
|
#define USB_STALL_SENT 20
|
|
|
|
|
#define USB_IN_NAK_SENT 19
|
|
|
|
|
#define USB_IN_ACK_RCVD 18
|
|
|
|
|
#define USB_OUT_PING_NAK_SENT 17
|
|
|
|
|
#define USB_OUT_ACK_SENT 16
|
|
|
|
|
#define FIFO_OVERFLOW 13
|
|
|
|
|
#define FIFO_UNDERFLOW 12
|
|
|
|
|
#define FIFO_FULL 11
|
|
|
|
|
#define FIFO_EMPTY 10
|
|
|
|
|
#define FIFO_FLUSH 9
|
|
|
|
|
#define SHORT_PACKET_OUT_DONE_INTERRUPT 6
|
|
|
|
|
#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5
|
|
|
|
|
#define NAK_OUT_PACKETS 4
|
|
|
|
|
#define DATA_PACKET_RECEIVED_INTERRUPT 3
|
|
|
|
|
#define DATA_PACKET_TRANSMITTED_INTERRUPT 2
|
|
|
|
|
#define DATA_OUT_PING_TOKEN_INTERRUPT 1
|
|
|
|
|
#define DATA_IN_TOKEN_INTERRUPT 0
|
2008-01-31 06:21:33 +07:00
|
|
|
/* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */
|
2006-04-03 01:21:26 +07:00
|
|
|
u32 ep_avail;
|
|
|
|
|
u32 ep_data;
|
|
|
|
|
u32 _unused0 [2];
|
|
|
|
|
} __attribute__ ((packed));
|
|
|
|
|
|
|
|
|
|
#endif /* __LINUX_USB_NET2280_H */
|
