2012-08-20 16:26:39 +07:00
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/*
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* QorIQ 10G MDIO Controller
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Authors: Andy Fleming <afleming@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/mdio.h>
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2013-09-18 02:28:33 +07:00
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#include <linux/of_address.h>
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2012-08-20 16:26:39 +07:00
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#include <linux/of_platform.h>
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#include <linux/of_mdio.h>
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/* Number of microseconds to wait for a register to respond */
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#define TIMEOUT 1000
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struct tgec_mdio_controller {
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__be32 reserved[12];
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__be32 mdio_stat; /* MDIO configuration and status */
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__be32 mdio_ctl; /* MDIO control */
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__be32 mdio_data; /* MDIO data */
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__be32 mdio_addr; /* MDIO address */
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} __packed;
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2015-01-04 16:36:02 +07:00
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#define MDIO_STAT_ENC BIT(6)
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2012-08-20 16:26:39 +07:00
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#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
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2015-01-13 09:30:59 +07:00
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#define MDIO_STAT_BSY BIT(0)
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#define MDIO_STAT_RD_ER BIT(1)
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2012-08-20 16:26:39 +07:00
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#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
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#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
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2015-01-13 09:30:59 +07:00
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#define MDIO_CTL_PRE_DIS BIT(10)
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#define MDIO_CTL_SCAN_EN BIT(11)
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#define MDIO_CTL_POST_INC BIT(14)
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#define MDIO_CTL_READ BIT(15)
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2012-08-20 16:26:39 +07:00
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#define MDIO_DATA(x) (x & 0xffff)
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2015-01-13 09:30:59 +07:00
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#define MDIO_DATA_BSY BIT(31)
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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struct mdio_fsl_priv {
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struct tgec_mdio_controller __iomem *mdio_base;
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bool is_little_endian;
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};
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static u32 xgmac_read32(void __iomem *regs,
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bool is_little_endian)
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{
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if (is_little_endian)
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return ioread32(regs);
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else
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return ioread32be(regs);
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}
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static void xgmac_write32(u32 value,
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void __iomem *regs,
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bool is_little_endian)
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{
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if (is_little_endian)
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iowrite32(value, regs);
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else
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iowrite32be(value, regs);
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}
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2012-08-20 16:26:39 +07:00
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/*
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2014-07-30 02:47:25 +07:00
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* Wait until the MDIO bus is free
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2012-08-20 16:26:39 +07:00
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*/
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static int xgmac_wait_until_free(struct device *dev,
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2015-03-16 17:56:29 +07:00
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struct tgec_mdio_controller __iomem *regs,
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bool is_little_endian)
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2012-08-20 16:26:39 +07:00
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{
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2015-01-21 18:08:32 +07:00
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unsigned int timeout;
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2012-08-20 16:26:39 +07:00
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/* Wait till the bus is free */
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2015-01-21 18:08:32 +07:00
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timeout = TIMEOUT;
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2015-03-16 17:56:29 +07:00
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while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
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MDIO_STAT_BSY) && timeout) {
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2015-01-21 18:08:32 +07:00
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cpu_relax();
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timeout--;
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}
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if (!timeout) {
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2012-08-20 16:26:39 +07:00
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dev_err(dev, "timeout waiting for bus to be free\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Wait till the MDIO read or write operation is complete
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*/
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static int xgmac_wait_until_done(struct device *dev,
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2015-03-16 17:56:29 +07:00
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struct tgec_mdio_controller __iomem *regs,
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bool is_little_endian)
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2012-08-20 16:26:39 +07:00
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{
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2015-01-21 18:08:32 +07:00
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unsigned int timeout;
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2012-08-20 16:26:39 +07:00
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/* Wait till the MDIO write is complete */
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2015-01-21 18:08:32 +07:00
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timeout = TIMEOUT;
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2015-03-16 17:56:29 +07:00
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while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
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MDIO_STAT_BSY) && timeout) {
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2015-01-21 18:08:32 +07:00
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cpu_relax();
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timeout--;
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}
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if (!timeout) {
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2012-08-20 16:26:39 +07:00
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dev_err(dev, "timeout waiting for operation to complete\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Write value to the PHY for this device to the register at regnum,waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs.
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*/
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static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
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{
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2015-03-16 17:56:29 +07:00
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struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
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struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
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2015-01-04 16:36:02 +07:00
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uint16_t dev_addr;
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u32 mdio_ctl, mdio_stat;
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2012-08-20 16:26:39 +07:00
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int ret;
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2015-03-16 17:56:29 +07:00
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bool endian = priv->is_little_endian;
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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mdio_stat = xgmac_read32(®s->mdio_stat, endian);
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2015-01-04 16:36:02 +07:00
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if (regnum & MII_ADDR_C45) {
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/* Clause 45 (ie 10G) */
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dev_addr = (regnum >> 16) & 0x1f;
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mdio_stat |= MDIO_STAT_ENC;
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} else {
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/* Clause 22 (ie 1G) */
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dev_addr = regnum & 0x1f;
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mdio_stat &= ~MDIO_STAT_ENC;
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}
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_free(&bus->dev, regs, endian);
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2012-08-20 16:26:39 +07:00
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if (ret)
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return ret;
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2015-01-04 16:36:02 +07:00
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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2015-03-16 17:56:29 +07:00
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xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
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2015-01-04 16:36:02 +07:00
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/* Set the register address */
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if (regnum & MII_ADDR_C45) {
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2015-03-16 17:56:29 +07:00
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xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
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2015-01-04 16:36:02 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_free(&bus->dev, regs, endian);
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2015-01-04 16:36:02 +07:00
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if (ret)
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return ret;
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}
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2012-08-20 16:26:39 +07:00
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/* Write the value to the register */
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2015-03-16 17:56:29 +07:00
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xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_done(&bus->dev, regs, endian);
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2012-08-20 16:26:39 +07:00
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs.
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*/
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static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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2015-03-16 17:56:29 +07:00
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struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
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struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
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2015-01-04 16:36:02 +07:00
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uint16_t dev_addr;
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uint32_t mdio_stat;
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2012-08-20 16:26:39 +07:00
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uint32_t mdio_ctl;
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uint16_t value;
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int ret;
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2015-03-16 17:56:29 +07:00
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bool endian = priv->is_little_endian;
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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mdio_stat = xgmac_read32(®s->mdio_stat, endian);
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2015-01-04 16:36:02 +07:00
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if (regnum & MII_ADDR_C45) {
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dev_addr = (regnum >> 16) & 0x1f;
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mdio_stat |= MDIO_STAT_ENC;
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} else {
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dev_addr = regnum & 0x1f;
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2015-01-13 09:30:31 +07:00
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mdio_stat &= ~MDIO_STAT_ENC;
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2015-01-04 16:36:02 +07:00
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}
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2015-03-16 17:56:29 +07:00
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xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
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2015-01-04 16:36:02 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_free(&bus->dev, regs, endian);
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2015-01-04 16:36:02 +07:00
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if (ret)
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return ret;
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2012-08-20 16:26:39 +07:00
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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2015-03-16 17:56:29 +07:00
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xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
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2012-08-20 16:26:39 +07:00
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/* Set the register address */
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2015-01-04 16:36:02 +07:00
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if (regnum & MII_ADDR_C45) {
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2015-03-16 17:56:29 +07:00
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xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_free(&bus->dev, regs, endian);
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2015-01-04 16:36:02 +07:00
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if (ret)
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return ret;
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}
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2012-08-20 16:26:39 +07:00
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/* Initiate the read */
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2015-03-16 17:56:29 +07:00
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xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
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2012-08-20 16:26:39 +07:00
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2015-03-16 17:56:29 +07:00
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ret = xgmac_wait_until_done(&bus->dev, regs, endian);
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2012-08-20 16:26:39 +07:00
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if (ret)
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return ret;
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/* Return all Fs if nothing was there */
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2015-03-16 17:56:29 +07:00
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if (xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) {
|
2014-06-12 01:41:40 +07:00
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dev_err(&bus->dev,
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2014-07-30 02:53:03 +07:00
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"Error while reading PHY%d reg at %d.%hhu\n",
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2014-06-12 01:41:40 +07:00
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phy_id, dev_addr, regnum);
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2012-08-20 16:26:39 +07:00
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return 0xffff;
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}
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|
2015-03-16 17:56:29 +07:00
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value = xgmac_read32(®s->mdio_data, endian) & 0xffff;
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2012-08-20 16:26:39 +07:00
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dev_dbg(&bus->dev, "read %04x\n", value);
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return value;
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}
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|
2012-12-03 21:23:58 +07:00
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static int xgmac_mdio_probe(struct platform_device *pdev)
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2012-08-20 16:26:39 +07:00
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{
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struct device_node *np = pdev->dev.of_node;
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struct mii_bus *bus;
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struct resource res;
|
2015-03-16 17:56:29 +07:00
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struct mdio_fsl_priv *priv;
|
2012-08-20 16:26:39 +07:00
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int ret;
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ret = of_address_to_resource(np, 0, &res);
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if (ret) {
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dev_err(&pdev->dev, "could not obtain address\n");
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return ret;
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}
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|
2015-03-16 17:56:29 +07:00
|
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bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
|
2012-08-20 16:26:39 +07:00
|
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if (!bus)
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return -ENOMEM;
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bus->name = "Freescale XGMAC MDIO Bus";
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bus->read = xgmac_mdio_read;
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bus->write = xgmac_mdio_write;
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bus->parent = &pdev->dev;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
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/* Set the PHY base address */
|
2015-03-16 17:56:29 +07:00
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priv = bus->priv;
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priv->mdio_base = of_iomap(np, 0);
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if (!priv->mdio_base) {
|
2012-08-20 16:26:39 +07:00
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ret = -ENOMEM;
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goto err_ioremap;
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}
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|
2015-03-16 17:56:29 +07:00
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if (of_get_property(pdev->dev.of_node,
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"little-endian", NULL))
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priv->is_little_endian = true;
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else
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priv->is_little_endian = false;
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|
2012-08-20 16:26:39 +07:00
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ret = of_mdiobus_register(bus, np);
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if (ret) {
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dev_err(&pdev->dev, "cannot register MDIO bus\n");
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goto err_registration;
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}
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|
2013-05-23 07:52:31 +07:00
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platform_set_drvdata(pdev, bus);
|
2012-08-20 16:26:39 +07:00
|
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return 0;
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err_registration:
|
2015-03-16 17:56:29 +07:00
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iounmap(priv->mdio_base);
|
2012-08-20 16:26:39 +07:00
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err_ioremap:
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mdiobus_free(bus);
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|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-03 21:23:58 +07:00
|
|
|
static int xgmac_mdio_remove(struct platform_device *pdev)
|
2012-08-20 16:26:39 +07:00
|
|
|
{
|
2013-05-23 07:52:31 +07:00
|
|
|
struct mii_bus *bus = platform_get_drvdata(pdev);
|
2012-08-20 16:26:39 +07:00
|
|
|
|
|
|
|
mdiobus_unregister(bus);
|
|
|
|
iounmap(bus->priv);
|
|
|
|
mdiobus_free(bus);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-18 01:37:34 +07:00
|
|
|
static const struct of_device_id xgmac_mdio_match[] = {
|
2012-08-20 16:26:39 +07:00
|
|
|
{
|
|
|
|
.compatible = "fsl,fman-xmdio",
|
|
|
|
},
|
2015-01-04 16:36:02 +07:00
|
|
|
{
|
|
|
|
.compatible = "fsl,fman-memac-mdio",
|
|
|
|
},
|
2012-08-20 16:26:39 +07:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
|
|
|
|
|
|
|
|
static struct platform_driver xgmac_mdio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "fsl-fman_xmdio",
|
|
|
|
.of_match_table = xgmac_mdio_match,
|
|
|
|
},
|
|
|
|
.probe = xgmac_mdio_probe,
|
|
|
|
.remove = xgmac_mdio_remove,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(xgmac_mdio_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
|
|
|
|
MODULE_LICENSE("GPL v2");
|