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linux_dsm_epyc7002/arch/mips/include/asm/asmmacro.h

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H
[PATCH] mips: nuke trailing whitespace Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-04 05:56:17 +07:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
#include <asm/hazards.h>
MIPS: Make local_irq_disable macro safe for non-Mipsr2 For non-mipsr2 processors, the local_irq_disable contains an mfc0-mtc0 pair with instructions inbetween. With preemption enabled, this sequence may get preempted and effect a stale value of CP0_STATUS when executing the mtc0 instruction. This commit avoids this scenario by incrementing the preempt count before the mfc0 and decrementing it after the mtc9. [ralf@linux-mips.org: This patch is sorting out the part that were missed by e97c5b6098 [MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus.] I also re-enabled the inclusion of <asm/asm-offsets.h> at the top of <asm/asmmacro.h>]. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-28 03:34:50 +07:00
#include <asm/asm-offsets.h>
MIPS: save/restore MSACSR register on context switch I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 22:44:28 +07:00
#include <asm/msa.h>
[PATCH] mips: nuke trailing whitespace Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-04 05:56:17 +07:00
[PATCH] mips: clean up 32/64-bit configuration Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-04 05:56:16 +07:00
#ifdef CONFIG_32BIT
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
#include <asm/asmmacro-32.h>
#endif
[PATCH] mips: clean up 32/64-bit configuration Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-04 05:56:16 +07:00
#ifdef CONFIG_64BIT
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
#include <asm/asmmacro-64.h>
#endif
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variants EI/DI instructions are available in MIPS R6 so add the needed definitions. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-05 19:56:40 +07:00
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
MIPS: Use EI/DI for MIPS R2. For MIPS R2, use the EI and DI instructions to enable and disable interrupts. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-12-10 23:37:25 +07:00
.macro local_irq_enable reg=t0
ei
irq_enable_hazard
.endm
.macro local_irq_disable reg=t0
di
irq_disable_hazard
.endm
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
#else
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_enable_hazard
.endm
.macro local_irq_disable reg=t0
MIPS: Make local_irq_disable macro safe for non-Mipsr2 For non-mipsr2 processors, the local_irq_disable contains an mfc0-mtc0 pair with instructions inbetween. With preemption enabled, this sequence may get preempted and effect a stale value of CP0_STATUS when executing the mtc0 instruction. This commit avoids this scenario by incrementing the preempt count before the mfc0 and decrementing it after the mtc9. [ralf@linux-mips.org: This patch is sorting out the part that were missed by e97c5b6098 [MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus.] I also re-enabled the inclusion of <asm/asm-offsets.h> at the top of <asm/asmmacro.h>]. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-28 03:34:50 +07:00
#ifdef CONFIG_PREEMPT
lw \reg, TI_PRE_COUNT($28)
addi \reg, \reg, 1
sw \reg, TI_PRE_COUNT($28)
#endif
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
xori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_disable_hazard
MIPS: Make local_irq_disable macro safe for non-Mipsr2 For non-mipsr2 processors, the local_irq_disable contains an mfc0-mtc0 pair with instructions inbetween. With preemption enabled, this sequence may get preempted and effect a stale value of CP0_STATUS when executing the mtc0 instruction. This commit avoids this scenario by incrementing the preempt count before the mfc0 and decrementing it after the mtc9. [ralf@linux-mips.org: This patch is sorting out the part that were missed by e97c5b6098 [MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus.] I also re-enabled the inclusion of <asm/asm-offsets.h> at the top of <asm/asmmacro.h>]. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/6164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-28 03:34:50 +07:00
#ifdef CONFIG_PREEMPT
lw \reg, TI_PRE_COUNT($28)
addi \reg, \reg, -1
sw \reg, TI_PRE_COUNT($28)
#endif
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
.endm
MIPS: MT: Remove SMTC support Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-23 21:29:44 +07:00
#endif /* CONFIG_CPU_MIPSR2 */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
.macro fpu_save_16even thread tmp=t0
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
.set push
SET_HARDFLOAT
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
cfc1 \tmp, fcr31
MIPS: Don't assume 64-bit FP registers for context switch When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:08 +07:00
sdc1 $f0, THREAD_FPR0_LS64(\thread)
sdc1 $f2, THREAD_FPR2_LS64(\thread)
sdc1 $f4, THREAD_FPR4_LS64(\thread)
sdc1 $f6, THREAD_FPR6_LS64(\thread)
sdc1 $f8, THREAD_FPR8_LS64(\thread)
sdc1 $f10, THREAD_FPR10_LS64(\thread)
sdc1 $f12, THREAD_FPR12_LS64(\thread)
sdc1 $f14, THREAD_FPR14_LS64(\thread)
sdc1 $f16, THREAD_FPR16_LS64(\thread)
sdc1 $f18, THREAD_FPR18_LS64(\thread)
sdc1 $f20, THREAD_FPR20_LS64(\thread)
sdc1 $f22, THREAD_FPR22_LS64(\thread)
sdc1 $f24, THREAD_FPR24_LS64(\thread)
sdc1 $f26, THREAD_FPR26_LS64(\thread)
sdc1 $f28, THREAD_FPR28_LS64(\thread)
sdc1 $f30, THREAD_FPR30_LS64(\thread)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
sw \tmp, THREAD_FCR31(\thread)
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
.set pop
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
.endm
.macro fpu_save_16odd thread
.set push
.set mips64r2
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Don't assume 64-bit FP registers for context switch When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:08 +07:00
sdc1 $f1, THREAD_FPR1_LS64(\thread)
sdc1 $f3, THREAD_FPR3_LS64(\thread)
sdc1 $f5, THREAD_FPR5_LS64(\thread)
sdc1 $f7, THREAD_FPR7_LS64(\thread)
sdc1 $f9, THREAD_FPR9_LS64(\thread)
sdc1 $f11, THREAD_FPR11_LS64(\thread)
sdc1 $f13, THREAD_FPR13_LS64(\thread)
sdc1 $f15, THREAD_FPR15_LS64(\thread)
sdc1 $f17, THREAD_FPR17_LS64(\thread)
sdc1 $f19, THREAD_FPR19_LS64(\thread)
sdc1 $f21, THREAD_FPR21_LS64(\thread)
sdc1 $f23, THREAD_FPR23_LS64(\thread)
sdc1 $f25, THREAD_FPR25_LS64(\thread)
sdc1 $f27, THREAD_FPR27_LS64(\thread)
sdc1 $f29, THREAD_FPR29_LS64(\thread)
sdc1 $f31, THREAD_FPR31_LS64(\thread)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
.set pop
.endm
.macro fpu_save_double thread status tmp
MIPS: kernel: r4k_switch: Add support for MIPS R6 Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 18:54:19 +07:00
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
defined(CONFIG_CPU_MIPS32_R6)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
10:
#endif
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
.set push
SET_HARDFLOAT
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
lw \tmp, THREAD_FCR31(\thread)
MIPS: Don't assume 64-bit FP registers for context switch When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:08 +07:00
ldc1 $f0, THREAD_FPR0_LS64(\thread)
ldc1 $f2, THREAD_FPR2_LS64(\thread)
ldc1 $f4, THREAD_FPR4_LS64(\thread)
ldc1 $f6, THREAD_FPR6_LS64(\thread)
ldc1 $f8, THREAD_FPR8_LS64(\thread)
ldc1 $f10, THREAD_FPR10_LS64(\thread)
ldc1 $f12, THREAD_FPR12_LS64(\thread)
ldc1 $f14, THREAD_FPR14_LS64(\thread)
ldc1 $f16, THREAD_FPR16_LS64(\thread)
ldc1 $f18, THREAD_FPR18_LS64(\thread)
ldc1 $f20, THREAD_FPR20_LS64(\thread)
ldc1 $f22, THREAD_FPR22_LS64(\thread)
ldc1 $f24, THREAD_FPR24_LS64(\thread)
ldc1 $f26, THREAD_FPR26_LS64(\thread)
ldc1 $f28, THREAD_FPR28_LS64(\thread)
ldc1 $f30, THREAD_FPR30_LS64(\thread)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_16odd thread
.set push
.set mips64r2
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Don't assume 64-bit FP registers for context switch When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:08 +07:00
ldc1 $f1, THREAD_FPR1_LS64(\thread)
ldc1 $f3, THREAD_FPR3_LS64(\thread)
ldc1 $f5, THREAD_FPR5_LS64(\thread)
ldc1 $f7, THREAD_FPR7_LS64(\thread)
ldc1 $f9, THREAD_FPR9_LS64(\thread)
ldc1 $f11, THREAD_FPR11_LS64(\thread)
ldc1 $f13, THREAD_FPR13_LS64(\thread)
ldc1 $f15, THREAD_FPR15_LS64(\thread)
ldc1 $f17, THREAD_FPR17_LS64(\thread)
ldc1 $f19, THREAD_FPR19_LS64(\thread)
ldc1 $f21, THREAD_FPR21_LS64(\thread)
ldc1 $f23, THREAD_FPR23_LS64(\thread)
ldc1 $f25, THREAD_FPR25_LS64(\thread)
ldc1 $f27, THREAD_FPR27_LS64(\thread)
ldc1 $f29, THREAD_FPR29_LS64(\thread)
ldc1 $f31, THREAD_FPR31_LS64(\thread)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
.set pop
.endm
.macro fpu_restore_double thread status tmp
MIPS: kernel: r4k_switch: Add support for MIPS R6 Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 18:54:19 +07:00
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
defined(CONFIG_CPU_MIPS32_R6)
MIPS: Support for 64-bit FP with O32 binaries CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-22 20:12:07 +07:00
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?
fpu_restore_16odd \thread
10:
#endif
fpu_restore_16even \thread \tmp
.endm
MIPS: kernel: r4k_switch: Add support for MIPS R6 Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 18:54:19 +07:00
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
MIPS: Introduce _EXT assembler macro This patch adds a simple macro to wrap the ext instruction which was introduced with MIPSR2, and fall back to a shift & and pair for pre-MIPSR2 CPUs. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6358/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-15 17:31:49 +07:00
.macro _EXT rd, rs, p, s
ext \rd, \rs, \p, \s
.endm
MIPS: kernel: r4k_switch: Add support for MIPS R6 Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 18:54:19 +07:00
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
MIPS: Introduce _EXT assembler macro This patch adds a simple macro to wrap the ext instruction which was introduced with MIPSR2, and fall back to a shift & and pair for pre-MIPSR2 CPUs. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6358/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-15 17:31:49 +07:00
.macro _EXT rd, rs, p, s
srl \rd, \rs, \p
andi \rd, \rd, (1 << \s) - 1
.endm
MIPS: kernel: r4k_switch: Add support for MIPS R6 Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 18:54:19 +07:00
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
MIPS: Introduce _EXT assembler macro This patch adds a simple macro to wrap the ext instruction which was introduced with MIPSR2, and fall back to a shift & and pair for pre-MIPSR2 CPUs. This will be used in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6358/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-15 17:31:49 +07:00
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
/*
* Temporary until all gas have MT ASE support
*/
.macro DMT reg=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41600bc1 | (\reg << 16)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
.macro EMT reg=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41600be1 | (\reg << 16)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
.macro DVPE reg=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41600001 | (\reg << 16)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
.macro EVPE reg=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41600021 | (\reg << 16)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
.macro MFTR rt=0, rd=0, u=0, sel=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
.macro MTTR rt=0, rd=0, u=0, sel=0
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-12 05:46:15 +07:00
.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 15:45:45 +07:00
.endm
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
#ifdef TOOLCHAIN_SUPPORTS_MSA
.macro ld_d wd, off, base
.set push
.set mips32r2
.set msa
ld.d $w\wd, \off(\base)
.set pop
.endm
.macro st_d wd, off, base
.set push
.set mips32r2
.set msa
st.d $w\wd, \off(\base)
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro copy_u_w ws, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set mips32r2
.set msa
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
copy_u.w $1, $w\ws[\n]
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro copy_u_d ws, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set mips64r2
.set msa
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
copy_u.d $1, $w\ws[\n]
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro insert_w wd, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set mips32r2
.set msa
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
insert.w $w\wd[\n], $1
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro insert_d wd, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set mips64r2
.set msa
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
insert.d $w\wd[\n], $1
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
#else
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN 0x587e0056
#define CTC_MSA_INSN 0x583e0816
#define LDD_MSA_INSN 0x58000837
#define STD_MSA_INSN 0x5800083f
#define COPY_UW_MSA_INSN 0x58f00056
#define COPY_UD_MSA_INSN 0x58f80056
#define INSERT_W_MSA_INSN 0x59300816
#define INSERT_D_MSA_INSN 0x59380816
#else
#define CFC_MSA_INSN 0x787e0059
#define CTC_MSA_INSN 0x783e0819
#define LDD_MSA_INSN 0x78000823
#define STD_MSA_INSN 0x78000827
#define COPY_UW_MSA_INSN 0x78f00059
#define COPY_UD_MSA_INSN 0x78f80059
#define INSERT_W_MSA_INSN 0x79300819
#define INSERT_D_MSA_INSN 0x79380819
#endif
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
/*
* Temporary until all toolchains in use include MSA support.
*/
.macro cfcmsa rd, cs
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.insn
.word CFC_MSA_INSN | (\cs << 11)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
move \rd, $1
.set pop
.endm
.macro ctcmsa cd, rs
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
move $1, \rs
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.word CTC_MSA_INSN | (\cd << 6)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
.macro ld_d wd, off, base
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: asm: asmmacro: Replace "add" instructions with "addu" The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-05 21:17:52 +07:00
addu $1, \base, \off
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.word LDD_MSA_INSN | (\wd << 6)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
.macro st_d wd, off, base
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: asm: asmmacro: Replace "add" instructions with "addu" The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-05 21:17:52 +07:00
addu $1, \base, \off
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.word STD_MSA_INSN | (\wd << 6)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro copy_u_w ws, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.insn
.word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro copy_u_d ws, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.insn
.word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro insert_w wd, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
MIPS: assume at as source/dest of MSA copy/insert instructions Assuming at ($1) as the source or destination register of copy or insert instructions: - Simplifies the macros providing those instructions for toolchains without MSA support. - Avoids an unnecessary move instruction when at is used as the source or destination register anyway. - Is sufficient for the uses to be introduced in the kernel by a subsequent patch. Note that due to a patch ordering snafu on my part this also fixes the currently broken build with MSA support enabled. The build has been broken since commit c9017757c532 "MIPS: init upper 64b of vector registers when MSA is first used", which this patch should have preceeded. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 19:09:31 +07:00
.macro insert_d wd, n
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: Add microMIPS MSA support. This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-04-16 04:06:49 +07:00
.word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
MIPS: Add MSA register definitions & access This patch introduces definitions for the MSA control registers and functions which allow access to both the control & vector registers. If the toolchain being used to build the kernel includes support for MSA then this patch will make use of that support & use MSA instructions directly. However toolchain support for MSA is very new & far from a point where it can be reasonably expected that everyone building the kernel uses a toolchain with support. Thus fallbacks using .word assembler directives are also provided for now as a temporary measure. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6429/ Patchwork: https://patchwork.linux-mips.org/patch/6607/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:09 +07:00
.set pop
.endm
#endif
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:11 +07:00
.macro msa_save_all thread
st_d 0, THREAD_FPR0, \thread
st_d 1, THREAD_FPR1, \thread
st_d 2, THREAD_FPR2, \thread
st_d 3, THREAD_FPR3, \thread
st_d 4, THREAD_FPR4, \thread
st_d 5, THREAD_FPR5, \thread
st_d 6, THREAD_FPR6, \thread
st_d 7, THREAD_FPR7, \thread
st_d 8, THREAD_FPR8, \thread
st_d 9, THREAD_FPR9, \thread
st_d 10, THREAD_FPR10, \thread
st_d 11, THREAD_FPR11, \thread
st_d 12, THREAD_FPR12, \thread
st_d 13, THREAD_FPR13, \thread
st_d 14, THREAD_FPR14, \thread
st_d 15, THREAD_FPR15, \thread
st_d 16, THREAD_FPR16, \thread
st_d 17, THREAD_FPR17, \thread
st_d 18, THREAD_FPR18, \thread
st_d 19, THREAD_FPR19, \thread
st_d 20, THREAD_FPR20, \thread
st_d 21, THREAD_FPR21, \thread
st_d 22, THREAD_FPR22, \thread
st_d 23, THREAD_FPR23, \thread
st_d 24, THREAD_FPR24, \thread
st_d 25, THREAD_FPR25, \thread
st_d 26, THREAD_FPR26, \thread
st_d 27, THREAD_FPR27, \thread
st_d 28, THREAD_FPR28, \thread
st_d 29, THREAD_FPR29, \thread
st_d 30, THREAD_FPR30, \thread
st_d 31, THREAD_FPR31, \thread
MIPS: save/restore MSACSR register on context switch I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 22:44:28 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: save/restore MSACSR register on context switch I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 22:44:28 +07:00
cfcmsa $1, MSA_CSR
sw $1, THREAD_MSA_CSR(\thread)
.set pop
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:11 +07:00
.endm
.macro msa_restore_all thread
MIPS: save/restore MSACSR register on context switch I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 22:44:28 +07:00
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: save/restore MSACSR register on context switch I added a field for the MSACSR register in struct mips_fpu_struct, but never actually made use of it... This is a clear bug. Save and restore the MSACSR register along with the vector registers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7300/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 22:44:28 +07:00
lw $1, THREAD_MSA_CSR(\thread)
ctcmsa MSA_CSR, $1
.set pop
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 22:23:11 +07:00
ld_d 0, THREAD_FPR0, \thread
ld_d 1, THREAD_FPR1, \thread
ld_d 2, THREAD_FPR2, \thread
ld_d 3, THREAD_FPR3, \thread
ld_d 4, THREAD_FPR4, \thread
ld_d 5, THREAD_FPR5, \thread
ld_d 6, THREAD_FPR6, \thread
ld_d 7, THREAD_FPR7, \thread
ld_d 8, THREAD_FPR8, \thread
ld_d 9, THREAD_FPR9, \thread
ld_d 10, THREAD_FPR10, \thread
ld_d 11, THREAD_FPR11, \thread
ld_d 12, THREAD_FPR12, \thread
ld_d 13, THREAD_FPR13, \thread
ld_d 14, THREAD_FPR14, \thread
ld_d 15, THREAD_FPR15, \thread
ld_d 16, THREAD_FPR16, \thread
ld_d 17, THREAD_FPR17, \thread
ld_d 18, THREAD_FPR18, \thread
ld_d 19, THREAD_FPR19, \thread
ld_d 20, THREAD_FPR20, \thread
ld_d 21, THREAD_FPR21, \thread
ld_d 22, THREAD_FPR22, \thread
ld_d 23, THREAD_FPR23, \thread
ld_d 24, THREAD_FPR24, \thread
ld_d 25, THREAD_FPR25, \thread
ld_d 26, THREAD_FPR26, \thread
ld_d 27, THREAD_FPR27, \thread
ld_d 28, THREAD_FPR28, \thread
ld_d 29, THREAD_FPR29, \thread
ld_d 30, THREAD_FPR30, \thread
ld_d 31, THREAD_FPR31, \thread
.endm
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 14:53:20 +07:00
.macro msa_init_upper wd
#ifdef CONFIG_64BIT
insert_d \wd, 1
#else
insert_w \wd, 2
insert_w \wd, 3
#endif
.if 31-\wd
msa_init_upper (\wd+1)
.endif
.endm
.macro msa_init_all_upper
.set push
.set noat
MIPS: Fix build with binutils 2.24.51+ Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07 20:13:54 +07:00
SET_HARDFLOAT
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 14:53:20 +07:00
not $1, zero
msa_init_upper 0
.set pop
.endm
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 05:20:36 +07:00
#endif /* _ASM_ASMMACRO_H */
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