2011-07-03 12:56:22 +07:00
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "isci.h"
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2011-05-09 05:49:15 +07:00
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#include "host.h"
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2011-07-03 12:56:22 +07:00
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#include "phy.h"
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#include "scic_port.h"
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#include "scic_config_parameters.h"
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2011-03-03 03:31:24 +07:00
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struct scic_sds_phy;
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extern enum sci_status scic_sds_phy_start(struct scic_sds_phy *sci_phy);
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extern enum sci_status scic_sds_phy_stop(struct scic_sds_phy *sci_phy);
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2011-07-03 12:56:22 +07:00
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2011-05-07 07:36:38 +07:00
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void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
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2011-07-03 12:56:22 +07:00
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{
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2011-02-26 01:25:21 +07:00
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union scic_oem_parameters oem;
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2011-05-07 07:36:38 +07:00
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u64 sci_sas_addr;
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__be64 sas_addr;
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scic_oem_parameters_get(&ihost->sci, &oem);
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sci_sas_addr = oem.sds1.phys[index].sas_address.high;
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sci_sas_addr <<= 32;
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sci_sas_addr |= oem.sds1.phys[index].sas_address.low;
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sas_addr = cpu_to_be64(sci_sas_addr);
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memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
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iphy->isci_port = NULL;
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iphy->sas_phy.enabled = 0;
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iphy->sas_phy.id = index;
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iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
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iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
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iphy->sas_phy.ha = &ihost->sas_ha;
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iphy->sas_phy.lldd_phy = iphy;
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iphy->sas_phy.enabled = 1;
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iphy->sas_phy.class = SAS;
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iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
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iphy->sas_phy.tproto = 0;
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iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
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iphy->sas_phy.role = PHY_ROLE_INITIATOR;
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iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
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iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
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memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
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2011-07-03 12:56:22 +07:00
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}
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/**
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* isci_phy_control() - This function is one of the SAS Domain Template
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* functions. This is a phy management function.
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* @phy: This parameter specifies the sphy being controlled.
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* @func: This parameter specifies the phy control function being invoked.
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* @buf: This parameter is specific to the phy function being invoked.
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*
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* status, zero indicates success.
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*/
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2011-03-03 03:31:24 +07:00
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int isci_phy_control(struct asd_sas_phy *sas_phy,
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enum phy_func func,
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void *buf)
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2011-07-03 12:56:22 +07:00
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{
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2011-03-03 03:31:24 +07:00
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int ret = 0;
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struct isci_phy *iphy = sas_phy->lldd_phy;
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struct isci_port *iport = iphy->isci_port;
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struct isci_host *ihost = sas_phy->ha->lldd_ha;
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unsigned long flags;
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2011-07-03 12:56:22 +07:00
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2011-03-03 03:31:24 +07:00
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dev_dbg(&ihost->pdev->dev,
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"%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
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__func__, sas_phy, func, buf, iphy, iport);
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2011-07-03 12:56:22 +07:00
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switch (func) {
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2011-03-03 03:31:24 +07:00
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case PHY_FUNC_DISABLE:
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spin_lock_irqsave(&ihost->scic_lock, flags);
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2011-05-07 07:36:38 +07:00
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scic_sds_phy_stop(&iphy->sci);
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2011-03-03 03:31:24 +07:00
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spin_unlock_irqrestore(&ihost->scic_lock, flags);
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break;
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2011-07-03 12:56:22 +07:00
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case PHY_FUNC_LINK_RESET:
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2011-03-03 03:31:24 +07:00
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spin_lock_irqsave(&ihost->scic_lock, flags);
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2011-05-07 07:36:38 +07:00
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scic_sds_phy_stop(&iphy->sci);
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scic_sds_phy_start(&iphy->sci);
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2011-03-03 03:31:24 +07:00
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spin_unlock_irqrestore(&ihost->scic_lock, flags);
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break;
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case PHY_FUNC_HARD_RESET:
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if (!iport)
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return -ENODEV;
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2011-07-03 12:56:22 +07:00
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/* Perform the port reset. */
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2011-04-01 03:10:44 +07:00
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ret = isci_port_perform_hard_reset(ihost, iport, iphy);
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2011-07-03 12:56:22 +07:00
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break;
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default:
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2011-03-03 03:31:24 +07:00
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dev_dbg(&ihost->pdev->dev,
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"%s: phy %p; func %d NOT IMPLEMENTED!\n",
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__func__, sas_phy, func);
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ret = -ENOSYS;
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2011-07-03 12:56:22 +07:00
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break;
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}
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return ret;
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}
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