net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
/*
|
|
|
|
* net/dsa/slave.c - Slave device handling
|
dsa: add switch chip cascading support
The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips. This patch adds support
for multiple switch chips on a network interface.
An example topology for a 16-port device with an embedded CPU is as
follows:
+-----+ +--------+ +--------+
| |eth0 10| switch |9 10| switch |
| CPU +----------+ +-------+ |
| | | chip 0 | | chip 1 |
+-----+ +---++---+ +---++---+
|| ||
|| ||
||1000baseT ||1000baseT
||ports 1-8 ||ports 9-16
This requires a couple of interdependent changes in the DSA layer:
- The dsa platform driver data needs to be extended: there is still
only one netdevice per DSA driver instance (eth0 in the example
above), but each of the switch chips in the tree needs its own
mii_bus device pointer, MII management bus address, and port name
array. (include/net/dsa.h) The existing in-tree dsa users need
some small changes to deal with this. (arch/arm)
- The DSA and Ethertype DSA tagging modules need to be extended to
use the DSA device ID field on receive and demultiplex the packet
accordingly, and fill in the DSA device ID field on transmit
according to which switch chip the packet is heading to.
(net/dsa/tag_{dsa,edsa}.c)
- The concept of "CPU port", which is the switch chip port that the
CPU is connected to (port 10 on switch chip 0 in the example), needs
to be extended with the concept of "upstream port", which is the
port on the switch chip that will bring us one hop closer to the CPU
(port 10 for both switch chips in the example above).
- The dsa platform data needs to specify which ports on which switch
chips are links to other switch chips, so that we can enable DSA
tagging mode on them. (For inter-switch links, we always use
non-EtherType DSA tagging, since it has lower overhead. The CPU
link uses dsa or edsa tagging depending on what the 'root' switch
chip supports.) This is done by specifying "dsa" for the given
port in the port array.
- The dsa platform data needs to be extended with information on via
which port to reach any given switch chip from any given switch chip.
This info is specified via the per-switch chip data struct ->rtable[]
array, which gives the nexthop ports for each of the other switches
in the tree.
For the example topology above, the dsa platform data would look
something like this:
static struct dsa_chip_data sw[2] = {
{
.mii_bus = &foo,
.sw_addr = 1,
.port_names[0] = "p1",
.port_names[1] = "p2",
.port_names[2] = "p3",
.port_names[3] = "p4",
.port_names[4] = "p5",
.port_names[5] = "p6",
.port_names[6] = "p7",
.port_names[7] = "p8",
.port_names[9] = "dsa",
.port_names[10] = "cpu",
.rtable = (s8 []){ -1, 9, },
}, {
.mii_bus = &foo,
.sw_addr = 2,
.port_names[0] = "p9",
.port_names[1] = "p10",
.port_names[2] = "p11",
.port_names[3] = "p12",
.port_names[4] = "p13",
.port_names[5] = "p14",
.port_names[6] = "p15",
.port_names[7] = "p16",
.port_names[10] = "dsa",
.rtable = (s8 []){ 10, -1, },
},
},
static struct dsa_platform_data pd = {
.netdev = &foo,
.nr_switches = 2,
.sw = sw,
};
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 16:52:09 +07:00
|
|
|
* Copyright (c) 2008-2009 Marvell Semiconductor
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/list.h>
|
2008-11-11 12:53:12 +07:00
|
|
|
#include <linux/etherdevice.h>
|
2015-02-25 04:15:33 +07:00
|
|
|
#include <linux/netdevice.h>
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
#include <linux/phy.h>
|
2014-10-18 06:02:13 +07:00
|
|
|
#include <linux/phy_fixed.h>
|
2018-05-11 03:17:36 +07:00
|
|
|
#include <linux/phylink.h>
|
2014-08-28 07:04:51 +07:00
|
|
|
#include <linux/of_net.h>
|
|
|
|
#include <linux/of_mdio.h>
|
2016-01-07 02:11:18 +07:00
|
|
|
#include <linux/mdio.h>
|
2015-02-25 04:15:33 +07:00
|
|
|
#include <net/rtnetlink.h>
|
2017-01-31 03:41:40 +07:00
|
|
|
#include <net/pkt_cls.h>
|
|
|
|
#include <net/tc_act/tc_mirred.h>
|
2015-02-25 04:15:33 +07:00
|
|
|
#include <linux/if_bridge.h>
|
2015-08-01 01:42:57 +07:00
|
|
|
#include <linux/netpoll.h>
|
2018-02-14 07:07:49 +07:00
|
|
|
#include <linux/ptp_classify.h>
|
2017-05-18 02:46:03 +07:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
#include "dsa_priv.h"
|
|
|
|
|
2017-01-31 03:41:40 +07:00
|
|
|
static bool dsa_slave_dev_check(struct net_device *dev);
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
/* slave mii_bus handling ***************************************************/
|
|
|
|
static int dsa_slave_phy_read(struct mii_bus *bus, int addr, int reg)
|
|
|
|
{
|
|
|
|
struct dsa_switch *ds = bus->priv;
|
|
|
|
|
2014-08-28 07:04:51 +07:00
|
|
|
if (ds->phys_mii_mask & (1 << addr))
|
2016-08-23 23:38:56 +07:00
|
|
|
return ds->ops->phy_read(ds, addr, reg);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
return 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_phy_write(struct mii_bus *bus, int addr, int reg, u16 val)
|
|
|
|
{
|
|
|
|
struct dsa_switch *ds = bus->priv;
|
|
|
|
|
2014-08-28 07:04:51 +07:00
|
|
|
if (ds->phys_mii_mask & (1 << addr))
|
2016-08-23 23:38:56 +07:00
|
|
|
return ds->ops->phy_write(ds, addr, reg, val);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dsa_slave_mii_bus_init(struct dsa_switch *ds)
|
|
|
|
{
|
|
|
|
ds->slave_mii_bus->priv = (void *)ds;
|
|
|
|
ds->slave_mii_bus->name = "dsa slave smi";
|
|
|
|
ds->slave_mii_bus->read = dsa_slave_phy_read;
|
|
|
|
ds->slave_mii_bus->write = dsa_slave_phy_write;
|
2016-06-08 06:32:38 +07:00
|
|
|
snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "dsa-%d.%d",
|
2017-11-04 06:05:21 +07:00
|
|
|
ds->dst->index, ds->index);
|
2016-05-11 04:27:23 +07:00
|
|
|
ds->slave_mii_bus->parent = ds->dev;
|
net: dsa: set slave MII bus PHY mask
When registering a mdio bus, Linux assumes than every port has a PHY and tries
to scan it. If a switch port has no PHY registered, DSA will fail to register
the slave MII bus. To fix this, set the slave MII bus PHY mask to the switch
PHYs mask.
As an example, if we use a Marvell MV88E6352 (which is a 7-port switch with no
registered PHYs for port 5 and port 6), with the following declared names:
static struct dsa_chip_data switch_cdata = {
[...]
.port_names[0] = "sw0",
.port_names[1] = "sw1",
.port_names[2] = "sw2",
.port_names[3] = "sw3",
.port_names[4] = "sw4",
.port_names[5] = "cpu",
};
DSA will fail to create the switch instance. With the PHY mask set for the
slave MII bus, only the PHY for ports 0-4 will be scanned and the instance will
be successfully created.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-21 07:13:32 +07:00
|
|
|
ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* slave device handling ****************************************************/
|
2015-04-02 22:07:08 +07:00
|
|
|
static int dsa_slave_get_iflink(const struct net_device *dev)
|
dsa: set ->iflink on slave interfaces to the ifindex of the parent
..so that we can parse the DSA topology from 'ip link' output:
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
3: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
4: lan1@eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue
5: lan2@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
6: lan3@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
7: lan4@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 16:49:49 +07:00
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
return dsa_slave_to_master(dev)->ifindex;
|
dsa: set ->iflink on slave interfaces to the ifindex of the parent
..so that we can parse the DSA topology from 'ip link' output:
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 16436 qdisc noqueue
2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
3: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast qlen 1000
4: lan1@eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc noqueue
5: lan2@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
6: lan3@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
7: lan4@eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc noqueue
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-03-20 16:49:49 +07:00
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
static int dsa_slave_open(struct net_device *dev)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2008-11-11 12:53:12 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!(master->flags & IFF_UP))
|
|
|
|
return -ENETDOWN;
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 01:56:57 +07:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr)) {
|
2010-04-02 04:22:09 +07:00
|
|
|
err = dev_uc_add(master, dev->dev_addr);
|
2008-11-11 12:53:12 +07:00
|
|
|
if (err < 0)
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->flags & IFF_ALLMULTI) {
|
|
|
|
err = dev_set_allmulti(master, 1);
|
|
|
|
if (err < 0)
|
|
|
|
goto del_unicast;
|
|
|
|
}
|
|
|
|
if (dev->flags & IFF_PROMISC) {
|
|
|
|
err = dev_set_promiscuity(master, 1);
|
|
|
|
if (err < 0)
|
|
|
|
goto clear_allmulti;
|
|
|
|
}
|
|
|
|
|
2017-09-27 04:15:32 +07:00
|
|
|
err = dsa_port_enable(dp, dev->phydev);
|
2017-09-23 06:01:56 +07:00
|
|
|
if (err)
|
|
|
|
goto clear_promisc;
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_start(dp->pl);
|
2014-09-25 07:05:17 +07:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
return 0;
|
2008-11-11 12:53:12 +07:00
|
|
|
|
2014-09-25 07:05:18 +07:00
|
|
|
clear_promisc:
|
|
|
|
if (dev->flags & IFF_PROMISC)
|
2015-06-25 20:50:13 +07:00
|
|
|
dev_set_promiscuity(master, -1);
|
2008-11-11 12:53:12 +07:00
|
|
|
clear_allmulti:
|
|
|
|
if (dev->flags & IFF_ALLMULTI)
|
|
|
|
dev_set_allmulti(master, -1);
|
|
|
|
del_unicast:
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 01:56:57 +07:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 04:22:09 +07:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 12:53:12 +07:00
|
|
|
out:
|
|
|
|
return err;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_close(struct net_device *dev)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2008-11-11 12:53:12 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_stop(dp->pl);
|
2014-09-25 07:05:17 +07:00
|
|
|
|
2019-02-25 02:44:43 +07:00
|
|
|
dsa_port_disable(dp);
|
2017-09-23 06:01:55 +07:00
|
|
|
|
2008-11-11 12:53:12 +07:00
|
|
|
dev_mc_unsync(master, dev);
|
2010-04-02 04:22:09 +07:00
|
|
|
dev_uc_unsync(master, dev);
|
2008-11-11 12:53:12 +07:00
|
|
|
if (dev->flags & IFF_ALLMULTI)
|
|
|
|
dev_set_allmulti(master, -1);
|
|
|
|
if (dev->flags & IFF_PROMISC)
|
|
|
|
dev_set_promiscuity(master, -1);
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 01:56:57 +07:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 04:22:09 +07:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 12:53:12 +07:00
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_change_rx_flags(struct net_device *dev, int change)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2019-02-02 21:29:35 +07:00
|
|
|
if (dev->flags & IFF_UP) {
|
|
|
|
if (change & IFF_ALLMULTI)
|
|
|
|
dev_set_allmulti(master,
|
|
|
|
dev->flags & IFF_ALLMULTI ? 1 : -1);
|
|
|
|
if (change & IFF_PROMISC)
|
|
|
|
dev_set_promiscuity(master,
|
|
|
|
dev->flags & IFF_PROMISC ? 1 : -1);
|
|
|
|
}
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_set_rx_mode(struct net_device *dev)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
dev_mc_sync(master, dev);
|
2010-04-02 04:22:09 +07:00
|
|
|
dev_uc_sync(master, dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
2008-11-11 12:53:12 +07:00
|
|
|
static int dsa_slave_set_mac_address(struct net_device *dev, void *a)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2008-11-11 12:53:12 +07:00
|
|
|
struct sockaddr *addr = a;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!is_valid_ether_addr(addr->sa_data))
|
|
|
|
return -EADDRNOTAVAIL;
|
|
|
|
|
|
|
|
if (!(dev->flags & IFF_UP))
|
|
|
|
goto out;
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 01:56:57 +07:00
|
|
|
if (!ether_addr_equal(addr->sa_data, master->dev_addr)) {
|
2010-04-02 04:22:09 +07:00
|
|
|
err = dev_uc_add(master, addr->sa_data);
|
2008-11-11 12:53:12 +07:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
dsa: Convert compare_ether_addr to ether_addr_equal
Use the new bool function ether_addr_equal to add
some clarity and reduce the likelihood for misuse
of compare_ether_addr for sorting.
Done via cocci script:
$ cat compare_ether_addr.cocci
@@
expression a,b;
@@
- !compare_ether_addr(a, b)
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- compare_ether_addr(a, b)
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) == 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !ether_addr_equal(a, b) != 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) == 0
+ !ether_addr_equal(a, b)
@@
expression a,b;
@@
- ether_addr_equal(a, b) != 0
+ ether_addr_equal(a, b)
@@
expression a,b;
@@
- !!ether_addr_equal(a, b)
+ ether_addr_equal(a, b)
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-05-09 01:56:57 +07:00
|
|
|
if (!ether_addr_equal(dev->dev_addr, master->dev_addr))
|
2010-04-02 04:22:09 +07:00
|
|
|
dev_uc_del(master, dev->dev_addr);
|
2008-11-11 12:53:12 +07:00
|
|
|
|
|
|
|
out:
|
2014-01-21 00:52:20 +07:00
|
|
|
ether_addr_copy(dev->dev_addr, addr->sa_data);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-08-06 20:15:49 +07:00
|
|
|
struct dsa_slave_dump_ctx {
|
|
|
|
struct net_device *dev;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct netlink_callback *cb;
|
|
|
|
int idx;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
dsa_slave_port_fdb_do_dump(const unsigned char *addr, u16 vid,
|
|
|
|
bool is_static, void *data)
|
|
|
|
{
|
|
|
|
struct dsa_slave_dump_ctx *dump = data;
|
|
|
|
u32 portid = NETLINK_CB(dump->cb->skb).portid;
|
|
|
|
u32 seq = dump->cb->nlh->nlmsg_seq;
|
|
|
|
struct nlmsghdr *nlh;
|
|
|
|
struct ndmsg *ndm;
|
|
|
|
|
|
|
|
if (dump->idx < dump->cb->args[2])
|
|
|
|
goto skip;
|
|
|
|
|
|
|
|
nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
|
|
|
|
sizeof(*ndm), NLM_F_MULTI);
|
|
|
|
if (!nlh)
|
|
|
|
return -EMSGSIZE;
|
|
|
|
|
|
|
|
ndm = nlmsg_data(nlh);
|
|
|
|
ndm->ndm_family = AF_BRIDGE;
|
|
|
|
ndm->ndm_pad1 = 0;
|
|
|
|
ndm->ndm_pad2 = 0;
|
|
|
|
ndm->ndm_flags = NTF_SELF;
|
|
|
|
ndm->ndm_type = 0;
|
|
|
|
ndm->ndm_ifindex = dump->dev->ifindex;
|
|
|
|
ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
|
|
|
|
|
|
|
|
if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
|
|
|
|
goto nla_put_failure;
|
|
|
|
|
|
|
|
if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
|
|
|
|
goto nla_put_failure;
|
|
|
|
|
|
|
|
nlmsg_end(dump->skb, nlh);
|
|
|
|
|
|
|
|
skip:
|
|
|
|
dump->idx++;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
nla_put_failure:
|
|
|
|
nlmsg_cancel(dump->skb, nlh);
|
|
|
|
return -EMSGSIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
dsa_slave_fdb_dump(struct sk_buff *skb, struct netlink_callback *cb,
|
|
|
|
struct net_device *dev, struct net_device *filter_dev,
|
|
|
|
int *idx)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-08-06 20:15:49 +07:00
|
|
|
struct dsa_slave_dump_ctx dump = {
|
|
|
|
.dev = dev,
|
|
|
|
.skb = skb,
|
|
|
|
.cb = cb,
|
|
|
|
.idx = *idx,
|
|
|
|
};
|
|
|
|
int err;
|
|
|
|
|
2017-09-21 06:32:14 +07:00
|
|
|
err = dsa_port_fdb_dump(dp, dsa_slave_port_fdb_do_dump, &dump);
|
2017-08-06 20:15:49 +07:00
|
|
|
*idx = dump.idx;
|
2017-09-21 06:32:14 +07:00
|
|
|
|
2017-08-06 20:15:49 +07:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
static int dsa_slave_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
|
|
{
|
2018-02-14 07:07:48 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
int port = p->dp->index;
|
|
|
|
|
|
|
|
/* Pass through to switch driver if it supports timestamping */
|
|
|
|
switch (cmd) {
|
|
|
|
case SIOCGHWTSTAMP:
|
|
|
|
if (ds->ops->port_hwtstamp_get)
|
|
|
|
return ds->ops->port_hwtstamp_get(ds, port, ifr);
|
|
|
|
break;
|
|
|
|
case SIOCSHWTSTAMP:
|
|
|
|
if (ds->ops->port_hwtstamp_set)
|
|
|
|
return ds->ops->port_hwtstamp_set(ds, port, ifr);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
return phylink_mii_ioctl(p->dp->pl, ifr, cmd);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
2015-05-10 23:47:51 +07:00
|
|
|
static int dsa_slave_port_attr_set(struct net_device *dev,
|
2015-10-15 00:40:49 +07:00
|
|
|
const struct switchdev_attr *attr,
|
2015-09-24 15:02:41 +07:00
|
|
|
struct switchdev_trans *trans)
|
2015-05-10 23:47:51 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-09-29 23:38:36 +07:00
|
|
|
int ret;
|
2015-05-10 23:47:51 +07:00
|
|
|
|
|
|
|
switch (attr->id) {
|
2015-10-01 16:03:42 +07:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
|
2017-05-20 04:00:36 +07:00
|
|
|
ret = dsa_port_set_state(dp, attr->u.stp_state, trans);
|
2015-05-10 23:47:51 +07:00
|
|
|
break;
|
2016-02-27 01:16:00 +07:00
|
|
|
case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
|
2017-05-20 04:00:42 +07:00
|
|
|
ret = dsa_port_vlan_filtering(dp, attr->u.vlan_filtering,
|
|
|
|
trans);
|
2016-02-27 01:16:00 +07:00
|
|
|
break;
|
2016-07-19 07:45:38 +07:00
|
|
|
case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
|
2017-05-20 04:00:43 +07:00
|
|
|
ret = dsa_port_ageing_time(dp, attr->u.ageing_time, trans);
|
2016-07-19 07:45:38 +07:00
|
|
|
break;
|
2019-02-21 07:58:22 +07:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS:
|
|
|
|
ret = dsa_port_pre_bridge_flags(dp, attr->u.brport_flags,
|
|
|
|
trans);
|
|
|
|
break;
|
2019-02-21 06:35:04 +07:00
|
|
|
case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
|
|
|
|
ret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans);
|
|
|
|
break;
|
2015-05-10 23:47:51 +07:00
|
|
|
default:
|
|
|
|
ret = -EOPNOTSUPP;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-08-10 20:09:53 +07:00
|
|
|
static int dsa_slave_port_obj_add(struct net_device *dev,
|
2015-10-01 16:03:45 +07:00
|
|
|
const struct switchdev_obj *obj,
|
2015-09-24 15:02:41 +07:00
|
|
|
struct switchdev_trans *trans)
|
2015-08-10 20:09:53 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-08-10 20:09:53 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
/* For the prepare phase, ensure the full set of changes is feasable in
|
|
|
|
* one go in order to signal a failure properly. If an operation is not
|
|
|
|
* supported, return -EOPNOTSUPP.
|
|
|
|
*/
|
|
|
|
|
2015-10-01 16:03:46 +07:00
|
|
|
switch (obj->id) {
|
2016-08-31 22:50:03 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_MDB:
|
2017-05-20 04:00:40 +07:00
|
|
|
err = dsa_port_mdb_add(dp, SWITCHDEV_OBJ_PORT_MDB(obj), trans);
|
2016-08-31 22:50:03 +07:00
|
|
|
break;
|
2017-11-10 05:11:00 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_HOST_MDB:
|
|
|
|
/* DSA can directly translate this to a normal MDB add,
|
|
|
|
* but on the CPU port.
|
|
|
|
*/
|
|
|
|
err = dsa_port_mdb_add(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj),
|
|
|
|
trans);
|
|
|
|
break;
|
2015-10-01 16:03:41 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_VLAN:
|
2017-05-20 04:00:41 +07:00
|
|
|
err = dsa_port_vlan_add(dp, SWITCHDEV_OBJ_PORT_VLAN(obj),
|
|
|
|
trans);
|
2015-08-13 23:52:17 +07:00
|
|
|
break;
|
2015-08-10 20:09:53 +07:00
|
|
|
default:
|
|
|
|
err = -EOPNOTSUPP;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_port_obj_del(struct net_device *dev,
|
2015-10-01 16:03:45 +07:00
|
|
|
const struct switchdev_obj *obj)
|
2015-08-10 20:09:53 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2015-08-10 20:09:53 +07:00
|
|
|
int err;
|
|
|
|
|
2015-10-01 16:03:46 +07:00
|
|
|
switch (obj->id) {
|
2016-08-31 22:50:03 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_MDB:
|
2017-05-20 04:00:40 +07:00
|
|
|
err = dsa_port_mdb_del(dp, SWITCHDEV_OBJ_PORT_MDB(obj));
|
2016-08-31 22:50:03 +07:00
|
|
|
break;
|
2017-11-10 05:11:00 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_HOST_MDB:
|
|
|
|
/* DSA can directly translate this to a normal MDB add,
|
|
|
|
* but on the CPU port.
|
|
|
|
*/
|
|
|
|
err = dsa_port_mdb_del(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj));
|
|
|
|
break;
|
2015-10-01 16:03:41 +07:00
|
|
|
case SWITCHDEV_OBJ_ID_PORT_VLAN:
|
2017-05-20 04:00:41 +07:00
|
|
|
err = dsa_port_vlan_del(dp, SWITCHDEV_OBJ_PORT_VLAN(obj));
|
2015-08-13 23:52:17 +07:00
|
|
|
break;
|
2015-08-10 20:09:53 +07:00
|
|
|
default:
|
|
|
|
err = -EOPNOTSUPP;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2019-02-07 00:45:45 +07:00
|
|
|
static int dsa_slave_get_port_parent_id(struct net_device *dev,
|
|
|
|
struct netdev_phys_item_id *ppid)
|
2015-02-25 04:15:33 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-11-10 04:29:51 +07:00
|
|
|
struct dsa_switch_tree *dst = ds->dst;
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2019-02-07 00:45:45 +07:00
|
|
|
ppid->id_len = sizeof(dst->index);
|
|
|
|
memcpy(&ppid->id, &dst->index, ppid->id_len);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-09-21 06:31:57 +07:00
|
|
|
static inline netdev_tx_t dsa_slave_netpoll_send_skb(struct net_device *dev,
|
|
|
|
struct sk_buff *skb)
|
2015-08-01 01:42:57 +07:00
|
|
|
{
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
2017-09-21 06:31:57 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
|
2015-08-01 01:42:57 +07:00
|
|
|
if (p->netpoll)
|
|
|
|
netpoll_send_skb(p->netpoll, skb);
|
|
|
|
#else
|
|
|
|
BUG();
|
|
|
|
#endif
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
}
|
|
|
|
|
2018-02-14 07:07:49 +07:00
|
|
|
static void dsa_skb_tx_timestamp(struct dsa_slave_priv *p,
|
|
|
|
struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
struct sk_buff *clone;
|
|
|
|
unsigned int type;
|
|
|
|
|
|
|
|
type = ptp_classify_raw(skb);
|
|
|
|
if (type == PTP_CLASS_NONE)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!ds->ops->port_txtstamp)
|
|
|
|
return;
|
|
|
|
|
|
|
|
clone = skb_clone_sk(skb);
|
|
|
|
if (!clone)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (ds->ops->port_txtstamp(ds, p->dp->index, clone, type))
|
|
|
|
return;
|
|
|
|
|
|
|
|
kfree_skb(clone);
|
|
|
|
}
|
|
|
|
|
2014-08-28 07:04:46 +07:00
|
|
|
static netdev_tx_t dsa_slave_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2017-08-04 11:33:27 +07:00
|
|
|
struct pcpu_sw_netstats *s;
|
2015-08-01 01:42:56 +07:00
|
|
|
struct sk_buff *nskb;
|
2014-08-28 07:04:46 +07:00
|
|
|
|
2017-08-04 11:33:27 +07:00
|
|
|
s = this_cpu_ptr(p->stats64);
|
|
|
|
u64_stats_update_begin(&s->syncp);
|
|
|
|
s->tx_packets++;
|
|
|
|
s->tx_bytes += skb->len;
|
|
|
|
u64_stats_update_end(&s->syncp);
|
2014-08-28 07:04:46 +07:00
|
|
|
|
2018-02-14 07:07:49 +07:00
|
|
|
/* Identify PTP protocol packets, clone them, and pass them to the
|
|
|
|
* switch driver
|
|
|
|
*/
|
|
|
|
dsa_skb_tx_timestamp(p, skb);
|
|
|
|
|
2017-06-02 03:07:15 +07:00
|
|
|
/* Transmit function may have to reallocate the original SKB,
|
|
|
|
* in which case it must have freed it. Only free it here on error.
|
|
|
|
*/
|
2015-08-01 01:42:56 +07:00
|
|
|
nskb = p->xmit(skb, dev);
|
2017-06-02 03:07:15 +07:00
|
|
|
if (!nskb) {
|
|
|
|
kfree_skb(skb);
|
2015-08-01 01:42:56 +07:00
|
|
|
return NETDEV_TX_OK;
|
2017-06-02 03:07:15 +07:00
|
|
|
}
|
2014-08-28 07:04:52 +07:00
|
|
|
|
2015-08-01 01:42:57 +07:00
|
|
|
/* SKB for netpoll still need to be mangled with the protocol-specific
|
|
|
|
* tag to be successfully transmitted
|
|
|
|
*/
|
|
|
|
if (unlikely(netpoll_tx_running(dev)))
|
2017-09-21 06:31:57 +07:00
|
|
|
return dsa_slave_netpoll_send_skb(dev, nskb);
|
2015-08-01 01:42:57 +07:00
|
|
|
|
2015-08-01 01:42:56 +07:00
|
|
|
/* Queue the SKB for transmission on the parent interface, but
|
|
|
|
* do not modify its EtherType
|
|
|
|
*/
|
2017-10-16 22:12:16 +07:00
|
|
|
nskb->dev = dsa_slave_to_master(dev);
|
2015-08-01 01:42:56 +07:00
|
|
|
dev_queue_xmit(nskb);
|
2014-08-28 07:04:52 +07:00
|
|
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
/* ethtool operations *******************************************************/
|
|
|
|
|
|
|
|
static void dsa_slave_get_drvinfo(struct net_device *dev,
|
|
|
|
struct ethtool_drvinfo *drvinfo)
|
|
|
|
{
|
2013-01-06 07:44:26 +07:00
|
|
|
strlcpy(drvinfo->driver, "dsa", sizeof(drvinfo->driver));
|
|
|
|
strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
|
|
|
|
strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
2014-10-30 00:45:04 +07:00
|
|
|
static int dsa_slave_get_regs_len(struct net_device *dev)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 00:45:04 +07:00
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_regs_len)
|
2017-10-16 22:12:15 +07:00
|
|
|
return ds->ops->get_regs_len(ds, dp->index);
|
2014-10-30 00:45:04 +07:00
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
dsa_slave_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 00:45:04 +07:00
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_regs)
|
2017-10-16 22:12:15 +07:00
|
|
|
ds->ops->get_regs(ds, dp->index, regs, _p);
|
2014-10-30 00:45:04 +07:00
|
|
|
}
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
static int dsa_slave_nway_reset(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
return phylink_ethtool_nway_reset(dp->pl);
|
|
|
|
}
|
|
|
|
|
2014-10-30 00:45:01 +07:00
|
|
|
static int dsa_slave_get_eeprom_len(struct net_device *dev)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 00:45:01 +07:00
|
|
|
|
2016-06-05 02:16:52 +07:00
|
|
|
if (ds->cd && ds->cd->eeprom_len)
|
2016-05-11 04:27:24 +07:00
|
|
|
return ds->cd->eeprom_len;
|
2014-10-30 00:45:01 +07:00
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_eeprom_len)
|
|
|
|
return ds->ops->get_eeprom_len(ds);
|
2014-10-30 00:45:01 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_get_eeprom(struct net_device *dev,
|
|
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 00:45:01 +07:00
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_eeprom)
|
|
|
|
return ds->ops->get_eeprom(ds, eeprom, data);
|
2014-10-30 00:45:01 +07:00
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_set_eeprom(struct net_device *dev,
|
|
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-10-30 00:45:01 +07:00
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->set_eeprom)
|
|
|
|
return ds->ops->set_eeprom(ds, eeprom, data);
|
2014-10-30 00:45:01 +07:00
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
static void dsa_slave_get_strings(struct net_device *dev,
|
|
|
|
uint32_t stringset, uint8_t *data)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
if (stringset == ETH_SS_STATS) {
|
|
|
|
int len = ETH_GSTRING_LEN;
|
|
|
|
|
|
|
|
strncpy(data, "tx_packets", len);
|
|
|
|
strncpy(data + len, "tx_bytes", len);
|
|
|
|
strncpy(data + 2 * len, "rx_packets", len);
|
|
|
|
strncpy(data + 3 * len, "rx_bytes", len);
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_strings)
|
2018-04-26 02:12:50 +07:00
|
|
|
ds->ops->get_strings(ds, dp->index, stringset,
|
|
|
|
data + 4 * len);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_get_ethtool_stats(struct net_device *dev,
|
|
|
|
struct ethtool_stats *stats,
|
|
|
|
uint64_t *data)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-08-04 11:33:27 +07:00
|
|
|
struct pcpu_sw_netstats *s;
|
2017-08-02 05:00:36 +07:00
|
|
|
unsigned int start;
|
2017-08-04 11:33:27 +07:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
u64 tx_packets, tx_bytes, rx_packets, rx_bytes;
|
|
|
|
|
|
|
|
s = per_cpu_ptr(p->stats64, i);
|
|
|
|
do {
|
|
|
|
start = u64_stats_fetch_begin_irq(&s->syncp);
|
|
|
|
tx_packets = s->tx_packets;
|
|
|
|
tx_bytes = s->tx_bytes;
|
|
|
|
rx_packets = s->rx_packets;
|
|
|
|
rx_bytes = s->rx_bytes;
|
|
|
|
} while (u64_stats_fetch_retry_irq(&s->syncp, start));
|
|
|
|
data[0] += tx_packets;
|
|
|
|
data[1] += tx_bytes;
|
|
|
|
data[2] += rx_packets;
|
|
|
|
data[3] += rx_bytes;
|
|
|
|
}
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_ethtool_stats)
|
2017-10-16 22:12:15 +07:00
|
|
|
ds->ops->get_ethtool_stats(ds, dp->index, data + 4);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_get_sset_count(struct net_device *dev, int sset)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
if (sset == ETH_SS_STATS) {
|
|
|
|
int count;
|
|
|
|
|
|
|
|
count = 4;
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_sset_count)
|
2018-04-26 02:12:50 +07:00
|
|
|
count += ds->ops->get_sset_count(ds, dp->index, sset);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
2014-09-19 07:31:24 +07:00
|
|
|
static void dsa_slave_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-19 07:31:24 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_ethtool_get_wol(dp->pl, w);
|
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_wol)
|
2017-10-16 22:12:15 +07:00
|
|
|
ds->ops->get_wol(ds, dp->index, w);
|
2014-09-19 07:31:24 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-19 07:31:24 +07:00
|
|
|
int ret = -EOPNOTSUPP;
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_ethtool_set_wol(dp->pl, w);
|
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->set_wol)
|
2017-10-16 22:12:15 +07:00
|
|
|
ret = ds->ops->set_wol(ds, dp->index, w);
|
2014-09-19 07:31:24 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-09-25 07:05:21 +07:00
|
|
|
static int dsa_slave_set_eee(struct net_device *dev, struct ethtool_eee *e)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-25 07:05:21 +07:00
|
|
|
int ret;
|
|
|
|
|
2017-08-02 03:32:31 +07:00
|
|
|
/* Port's PHY and MAC both need to be EEE capable */
|
2019-02-06 22:35:15 +07:00
|
|
|
if (!dev->phydev || !dp->pl)
|
2017-08-02 03:32:31 +07:00
|
|
|
return -ENODEV;
|
|
|
|
|
2017-08-02 03:32:41 +07:00
|
|
|
if (!ds->ops->set_mac_eee)
|
2014-09-25 07:05:21 +07:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
ret = ds->ops->set_mac_eee(ds, dp->index, e);
|
2014-09-25 07:05:21 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
return phylink_ethtool_set_eee(dp->pl, e);
|
2014-09-25 07:05:21 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_get_eee(struct net_device *dev, struct ethtool_eee *e)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-25 07:05:21 +07:00
|
|
|
int ret;
|
|
|
|
|
2017-08-02 03:32:31 +07:00
|
|
|
/* Port's PHY and MAC both need to be EEE capable */
|
2019-02-06 22:35:15 +07:00
|
|
|
if (!dev->phydev || !dp->pl)
|
2017-08-02 03:32:31 +07:00
|
|
|
return -ENODEV;
|
|
|
|
|
2017-08-02 03:32:41 +07:00
|
|
|
if (!ds->ops->get_mac_eee)
|
2014-09-25 07:05:21 +07:00
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
ret = ds->ops->get_mac_eee(ds, dp->index, e);
|
2014-09-25 07:05:21 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
return phylink_ethtool_get_eee(dp->pl, e);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_get_link_ksettings(struct net_device *dev,
|
|
|
|
struct ethtool_link_ksettings *cmd)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
return phylink_ethtool_ksettings_get(dp->pl, cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_set_link_ksettings(struct net_device *dev,
|
|
|
|
const struct ethtool_link_ksettings *cmd)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
return phylink_ethtool_ksettings_set(dp->pl, cmd);
|
2014-09-25 07:05:21 +07:00
|
|
|
}
|
|
|
|
|
2015-08-01 01:42:57 +07:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
static int dsa_slave_netpoll_setup(struct net_device *dev,
|
|
|
|
struct netpoll_info *ni)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2015-08-01 01:42:57 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
struct netpoll *netpoll;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
netpoll = kzalloc(sizeof(*netpoll), GFP_KERNEL);
|
|
|
|
if (!netpoll)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
err = __netpoll_setup(netpoll, master);
|
|
|
|
if (err) {
|
|
|
|
kfree(netpoll);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
p->netpoll = netpoll;
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_netpoll_cleanup(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
struct netpoll *netpoll = p->netpoll;
|
|
|
|
|
|
|
|
if (!netpoll)
|
|
|
|
return;
|
|
|
|
|
|
|
|
p->netpoll = NULL;
|
|
|
|
|
2018-10-18 22:18:26 +07:00
|
|
|
__netpoll_free(netpoll);
|
2015-08-01 01:42:57 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_poll_controller(struct net_device *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-01-11 03:32:36 +07:00
|
|
|
static int dsa_slave_get_phys_port_name(struct net_device *dev,
|
|
|
|
char *name, size_t len)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-11 03:32:36 +07:00
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
if (snprintf(name, len, "p%d", dp->index) >= len)
|
2017-01-11 03:32:36 +07:00
|
|
|
return -EINVAL;
|
2016-12-30 05:20:56 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-31 03:41:40 +07:00
|
|
|
static struct dsa_mall_tc_entry *
|
2017-09-21 06:31:57 +07:00
|
|
|
dsa_slave_mall_tc_entry_find(struct net_device *dev, unsigned long cookie)
|
2017-01-31 03:41:40 +07:00
|
|
|
{
|
2017-09-21 06:31:57 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2017-01-31 03:41:40 +07:00
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
|
|
|
|
|
|
|
list_for_each_entry(mall_tc_entry, &p->mall_tc_list, list)
|
|
|
|
if (mall_tc_entry->cookie == cookie)
|
|
|
|
return mall_tc_entry;
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_add_cls_matchall(struct net_device *dev,
|
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
bool ingress)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-31 03:41:40 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
2017-08-07 15:15:29 +07:00
|
|
|
__be16 protocol = cls->common.protocol;
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 03:41:40 +07:00
|
|
|
struct net_device *to_dev;
|
|
|
|
const struct tc_action *a;
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *to_dp;
|
2017-01-31 03:41:40 +07:00
|
|
|
int err = -EOPNOTSUPP;
|
|
|
|
|
|
|
|
if (!ds->ops->port_mirror_add)
|
|
|
|
return err;
|
|
|
|
|
2017-08-04 19:28:58 +07:00
|
|
|
if (!tcf_exts_has_one_action(cls->exts))
|
2017-01-31 03:41:40 +07:00
|
|
|
return err;
|
|
|
|
|
2018-08-20 02:22:09 +07:00
|
|
|
a = tcf_exts_first_action(cls->exts);
|
2017-01-31 03:41:40 +07:00
|
|
|
|
|
|
|
if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
|
|
|
|
struct dsa_mall_mirror_tc_entry *mirror;
|
|
|
|
|
2017-12-06 07:17:26 +07:00
|
|
|
to_dev = tcf_mirred_dev(a);
|
2017-01-31 03:41:40 +07:00
|
|
|
if (!to_dev)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!dsa_slave_dev_check(to_dev))
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
|
|
|
|
if (!mall_tc_entry)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mall_tc_entry->cookie = cls->cookie;
|
|
|
|
mall_tc_entry->type = DSA_PORT_MALL_MIRROR;
|
|
|
|
mirror = &mall_tc_entry->mirror;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
to_dp = dsa_slave_to_port(to_dev);
|
2017-01-31 03:41:40 +07:00
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
mirror->to_local_port = to_dp->index;
|
2017-01-31 03:41:40 +07:00
|
|
|
mirror->ingress = ingress;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
err = ds->ops->port_mirror_add(ds, dp->index, mirror, ingress);
|
2017-01-31 03:41:40 +07:00
|
|
|
if (err) {
|
|
|
|
kfree(mall_tc_entry);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
list_add_tail(&mall_tc_entry->list, &p->mall_tc_list);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_del_cls_matchall(struct net_device *dev,
|
|
|
|
struct tc_cls_matchall_offload *cls)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-01-31 03:41:40 +07:00
|
|
|
struct dsa_mall_tc_entry *mall_tc_entry;
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 03:41:40 +07:00
|
|
|
|
|
|
|
if (!ds->ops->port_mirror_del)
|
|
|
|
return;
|
|
|
|
|
2017-09-21 06:31:57 +07:00
|
|
|
mall_tc_entry = dsa_slave_mall_tc_entry_find(dev, cls->cookie);
|
2017-01-31 03:41:40 +07:00
|
|
|
if (!mall_tc_entry)
|
|
|
|
return;
|
|
|
|
|
|
|
|
list_del(&mall_tc_entry->list);
|
|
|
|
|
|
|
|
switch (mall_tc_entry->type) {
|
|
|
|
case DSA_PORT_MALL_MIRROR:
|
2017-10-16 22:12:15 +07:00
|
|
|
ds->ops->port_mirror_del(ds, dp->index, &mall_tc_entry->mirror);
|
2017-01-31 03:41:40 +07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN_ON(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
kfree(mall_tc_entry);
|
|
|
|
}
|
|
|
|
|
2017-08-07 15:15:26 +07:00
|
|
|
static int dsa_slave_setup_tc_cls_matchall(struct net_device *dev,
|
2017-10-19 20:50:45 +07:00
|
|
|
struct tc_cls_matchall_offload *cls,
|
|
|
|
bool ingress)
|
2017-01-31 03:41:40 +07:00
|
|
|
{
|
2017-08-07 15:15:29 +07:00
|
|
|
if (cls->common.chain_index)
|
2017-06-06 22:00:16 +07:00
|
|
|
return -EOPNOTSUPP;
|
2017-01-31 03:41:40 +07:00
|
|
|
|
2017-08-07 15:15:26 +07:00
|
|
|
switch (cls->command) {
|
|
|
|
case TC_CLSMATCHALL_REPLACE:
|
2017-08-07 15:15:29 +07:00
|
|
|
return dsa_slave_add_cls_matchall(dev, cls, ingress);
|
2017-08-07 15:15:26 +07:00
|
|
|
case TC_CLSMATCHALL_DESTROY:
|
|
|
|
dsa_slave_del_cls_matchall(dev, cls);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-19 20:50:45 +07:00
|
|
|
static int dsa_slave_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
|
|
|
|
void *cb_priv, bool ingress)
|
|
|
|
{
|
|
|
|
struct net_device *dev = cb_priv;
|
|
|
|
|
2017-11-01 17:47:39 +07:00
|
|
|
if (!tc_can_offload(dev))
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2017-10-19 20:50:45 +07:00
|
|
|
switch (type) {
|
|
|
|
case TC_SETUP_CLSMATCHALL:
|
|
|
|
return dsa_slave_setup_tc_cls_matchall(dev, type_data, ingress);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_block_cb_ig(enum tc_setup_type type,
|
|
|
|
void *type_data, void *cb_priv)
|
|
|
|
{
|
|
|
|
return dsa_slave_setup_tc_block_cb(type, type_data, cb_priv, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_block_cb_eg(enum tc_setup_type type,
|
|
|
|
void *type_data, void *cb_priv)
|
|
|
|
{
|
|
|
|
return dsa_slave_setup_tc_block_cb(type, type_data, cb_priv, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_setup_tc_block(struct net_device *dev,
|
|
|
|
struct tc_block_offload *f)
|
|
|
|
{
|
|
|
|
tc_setup_cb_t *cb;
|
|
|
|
|
|
|
|
if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
|
|
|
|
cb = dsa_slave_setup_tc_block_cb_ig;
|
|
|
|
else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
|
|
|
|
cb = dsa_slave_setup_tc_block_cb_eg;
|
|
|
|
else
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
switch (f->command) {
|
|
|
|
case TC_BLOCK_BIND:
|
2018-06-26 04:30:04 +07:00
|
|
|
return tcf_block_cb_register(f->block, cb, dev, dev, f->extack);
|
2017-10-19 20:50:45 +07:00
|
|
|
case TC_BLOCK_UNBIND:
|
|
|
|
tcf_block_cb_unregister(f->block, cb, dev);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-07 15:15:26 +07:00
|
|
|
static int dsa_slave_setup_tc(struct net_device *dev, enum tc_setup_type type,
|
2017-08-07 15:15:32 +07:00
|
|
|
void *type_data)
|
2017-08-07 15:15:26 +07:00
|
|
|
{
|
2017-08-07 15:15:17 +07:00
|
|
|
switch (type) {
|
2017-10-19 20:50:45 +07:00
|
|
|
case TC_SETUP_BLOCK:
|
|
|
|
return dsa_slave_setup_tc_block(dev, type_data);
|
2017-01-31 03:41:40 +07:00
|
|
|
default:
|
2017-06-06 22:00:16 +07:00
|
|
|
return -EOPNOTSUPP;
|
2017-01-31 03:41:40 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-08-02 05:00:36 +07:00
|
|
|
static void dsa_slave_get_stats64(struct net_device *dev,
|
|
|
|
struct rtnl_link_stats64 *stats)
|
|
|
|
{
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
2017-08-04 11:33:27 +07:00
|
|
|
struct pcpu_sw_netstats *s;
|
2017-08-02 05:00:36 +07:00
|
|
|
unsigned int start;
|
2017-08-04 11:33:27 +07:00
|
|
|
int i;
|
2017-08-02 05:00:36 +07:00
|
|
|
|
|
|
|
netdev_stats_to_stats64(stats, &dev->stats);
|
2017-08-04 11:33:27 +07:00
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
u64 tx_packets, tx_bytes, rx_packets, rx_bytes;
|
|
|
|
|
|
|
|
s = per_cpu_ptr(p->stats64, i);
|
|
|
|
do {
|
|
|
|
start = u64_stats_fetch_begin_irq(&s->syncp);
|
|
|
|
tx_packets = s->tx_packets;
|
|
|
|
tx_bytes = s->tx_bytes;
|
|
|
|
rx_packets = s->rx_packets;
|
|
|
|
rx_bytes = s->rx_bytes;
|
|
|
|
} while (u64_stats_fetch_retry_irq(&s->syncp, start));
|
|
|
|
|
|
|
|
stats->tx_packets += tx_packets;
|
|
|
|
stats->tx_bytes += tx_bytes;
|
|
|
|
stats->rx_packets += rx_packets;
|
|
|
|
stats->rx_bytes += rx_bytes;
|
|
|
|
}
|
2017-08-02 05:00:36 +07:00
|
|
|
}
|
|
|
|
|
2017-01-31 00:48:40 +07:00
|
|
|
static int dsa_slave_get_rxnfc(struct net_device *dev,
|
|
|
|
struct ethtool_rxnfc *nfc, u32 *rule_locs)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 00:48:40 +07:00
|
|
|
|
|
|
|
if (!ds->ops->get_rxnfc)
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
return ds->ops->get_rxnfc(ds, dp->index, nfc, rule_locs);
|
2017-01-31 00:48:40 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_set_rxnfc(struct net_device *dev,
|
|
|
|
struct ethtool_rxnfc *nfc)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2017-01-31 00:48:40 +07:00
|
|
|
|
|
|
|
if (!ds->ops->set_rxnfc)
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
return ds->ops->set_rxnfc(ds, dp->index, nfc);
|
2017-01-31 00:48:40 +07:00
|
|
|
}
|
|
|
|
|
2018-02-14 07:07:48 +07:00
|
|
|
static int dsa_slave_get_ts_info(struct net_device *dev,
|
|
|
|
struct ethtool_ts_info *ts)
|
|
|
|
{
|
|
|
|
struct dsa_slave_priv *p = netdev_priv(dev);
|
|
|
|
struct dsa_switch *ds = p->dp->ds;
|
|
|
|
|
|
|
|
if (!ds->ops->get_ts_info)
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
|
|
return ds->ops->get_ts_info(ds, p->dp->index, ts);
|
|
|
|
}
|
|
|
|
|
2019-02-21 05:35:39 +07:00
|
|
|
static int dsa_slave_vlan_rx_add_vid(struct net_device *dev, __be16 proto,
|
|
|
|
u16 vid)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct switchdev_obj_port_vlan vlan = {
|
|
|
|
.vid_begin = vid,
|
|
|
|
.vid_end = vid,
|
|
|
|
/* This API only allows programming tagged, non-PVID VIDs */
|
|
|
|
.flags = 0,
|
|
|
|
};
|
2019-03-02 01:37:25 +07:00
|
|
|
struct switchdev_trans trans;
|
2019-02-21 05:35:39 +07:00
|
|
|
struct bridge_vlan_info info;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Check for a possible bridge VLAN entry now since there is no
|
|
|
|
* need to emulate the switchdev prepare + commit phase.
|
|
|
|
*/
|
|
|
|
if (dp->bridge_dev) {
|
|
|
|
/* br_vlan_get_info() returns -EINVAL or -ENOENT if the
|
|
|
|
* device, respectively the VID is not found, returning
|
|
|
|
* 0 means success, which is a failure for us here.
|
|
|
|
*/
|
|
|
|
ret = br_vlan_get_info(dp->bridge_dev, vid, &info);
|
|
|
|
if (ret == 0)
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2019-03-02 01:37:25 +07:00
|
|
|
trans.ph_prepare = true;
|
|
|
|
ret = dsa_port_vlan_add(dp, &vlan, &trans);
|
2019-02-21 05:35:39 +07:00
|
|
|
if (ret == -EOPNOTSUPP)
|
2019-03-02 01:37:25 +07:00
|
|
|
return 0;
|
2019-02-21 05:35:39 +07:00
|
|
|
|
2019-03-02 01:37:25 +07:00
|
|
|
trans.ph_prepare = false;
|
|
|
|
return dsa_port_vlan_add(dp, &vlan, &trans);
|
2019-02-21 05:35:39 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_vlan_rx_kill_vid(struct net_device *dev, __be16 proto,
|
|
|
|
u16 vid)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct switchdev_obj_port_vlan vlan = {
|
|
|
|
.vid_begin = vid,
|
|
|
|
.vid_end = vid,
|
|
|
|
/* This API only allows programming tagged, non-PVID VIDs */
|
|
|
|
.flags = 0,
|
|
|
|
};
|
|
|
|
struct bridge_vlan_info info;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Check for a possible bridge VLAN entry now since there is no
|
|
|
|
* need to emulate the switchdev prepare + commit phase.
|
|
|
|
*/
|
|
|
|
if (dp->bridge_dev) {
|
|
|
|
/* br_vlan_get_info() returns -EINVAL or -ENOENT if the
|
|
|
|
* device, respectively the VID is not found, returning
|
|
|
|
* 0 means success, which is a failure for us here.
|
|
|
|
*/
|
|
|
|
ret = br_vlan_get_info(dp->bridge_dev, vid, &info);
|
|
|
|
if (ret == 0)
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = dsa_port_vlan_del(dp, &vlan);
|
|
|
|
if (ret == -EOPNOTSUPP)
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
static const struct ethtool_ops dsa_slave_ethtool_ops = {
|
|
|
|
.get_drvinfo = dsa_slave_get_drvinfo,
|
2014-10-30 00:45:04 +07:00
|
|
|
.get_regs_len = dsa_slave_get_regs_len,
|
|
|
|
.get_regs = dsa_slave_get_regs,
|
2018-05-11 03:17:36 +07:00
|
|
|
.nway_reset = dsa_slave_nway_reset,
|
2018-05-11 03:17:34 +07:00
|
|
|
.get_link = ethtool_op_get_link,
|
2014-10-30 00:45:01 +07:00
|
|
|
.get_eeprom_len = dsa_slave_get_eeprom_len,
|
|
|
|
.get_eeprom = dsa_slave_get_eeprom,
|
|
|
|
.set_eeprom = dsa_slave_set_eeprom,
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
.get_strings = dsa_slave_get_strings,
|
|
|
|
.get_ethtool_stats = dsa_slave_get_ethtool_stats,
|
|
|
|
.get_sset_count = dsa_slave_get_sset_count,
|
2014-09-19 07:31:24 +07:00
|
|
|
.set_wol = dsa_slave_set_wol,
|
|
|
|
.get_wol = dsa_slave_get_wol,
|
2014-09-25 07:05:21 +07:00
|
|
|
.set_eee = dsa_slave_set_eee,
|
|
|
|
.get_eee = dsa_slave_get_eee,
|
2018-05-11 03:17:36 +07:00
|
|
|
.get_link_ksettings = dsa_slave_get_link_ksettings,
|
|
|
|
.set_link_ksettings = dsa_slave_set_link_ksettings,
|
2017-01-31 00:48:40 +07:00
|
|
|
.get_rxnfc = dsa_slave_get_rxnfc,
|
|
|
|
.set_rxnfc = dsa_slave_set_rxnfc,
|
2018-02-14 07:07:48 +07:00
|
|
|
.get_ts_info = dsa_slave_get_ts_info,
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
};
|
|
|
|
|
2017-12-07 06:03:33 +07:00
|
|
|
/* legacy way, bypassing the bridge *****************************************/
|
|
|
|
int dsa_legacy_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
|
|
|
|
struct net_device *dev,
|
|
|
|
const unsigned char *addr, u16 vid,
|
2019-01-17 06:06:50 +07:00
|
|
|
u16 flags,
|
|
|
|
struct netlink_ext_ack *extack)
|
2017-12-07 06:03:33 +07:00
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
return dsa_port_fdb_add(dp, addr, vid);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dsa_legacy_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
|
|
|
|
struct net_device *dev,
|
|
|
|
const unsigned char *addr, u16 vid)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
|
|
|
|
return dsa_port_fdb_del(dp, addr, vid);
|
|
|
|
}
|
|
|
|
|
2014-08-28 07:04:46 +07:00
|
|
|
static const struct net_device_ops dsa_slave_netdev_ops = {
|
2009-01-07 07:45:26 +07:00
|
|
|
.ndo_open = dsa_slave_open,
|
|
|
|
.ndo_stop = dsa_slave_close,
|
2014-08-28 07:04:46 +07:00
|
|
|
.ndo_start_xmit = dsa_slave_xmit,
|
2009-01-07 07:45:26 +07:00
|
|
|
.ndo_change_rx_flags = dsa_slave_change_rx_flags,
|
|
|
|
.ndo_set_rx_mode = dsa_slave_set_rx_mode,
|
|
|
|
.ndo_set_mac_address = dsa_slave_set_mac_address,
|
2017-08-06 20:15:43 +07:00
|
|
|
.ndo_fdb_add = dsa_legacy_fdb_add,
|
|
|
|
.ndo_fdb_del = dsa_legacy_fdb_del,
|
2017-08-06 20:15:49 +07:00
|
|
|
.ndo_fdb_dump = dsa_slave_fdb_dump,
|
2009-01-07 07:45:26 +07:00
|
|
|
.ndo_do_ioctl = dsa_slave_ioctl,
|
2015-04-02 22:07:08 +07:00
|
|
|
.ndo_get_iflink = dsa_slave_get_iflink,
|
2015-08-01 01:42:57 +07:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
.ndo_netpoll_setup = dsa_slave_netpoll_setup,
|
|
|
|
.ndo_netpoll_cleanup = dsa_slave_netpoll_cleanup,
|
|
|
|
.ndo_poll_controller = dsa_slave_poll_controller,
|
|
|
|
#endif
|
2017-01-11 03:32:36 +07:00
|
|
|
.ndo_get_phys_port_name = dsa_slave_get_phys_port_name,
|
2017-01-31 03:41:40 +07:00
|
|
|
.ndo_setup_tc = dsa_slave_setup_tc,
|
2017-08-02 05:00:36 +07:00
|
|
|
.ndo_get_stats64 = dsa_slave_get_stats64,
|
2019-02-07 00:45:45 +07:00
|
|
|
.ndo_get_port_parent_id = dsa_slave_get_port_parent_id,
|
2019-02-21 05:35:39 +07:00
|
|
|
.ndo_vlan_rx_add_vid = dsa_slave_vlan_rx_add_vid,
|
|
|
|
.ndo_vlan_rx_kill_vid = dsa_slave_vlan_rx_kill_vid,
|
2015-03-16 11:07:15 +07:00
|
|
|
};
|
|
|
|
|
2015-09-24 08:19:58 +07:00
|
|
|
static struct device_type dsa_type = {
|
|
|
|
.name = "dsa",
|
|
|
|
};
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
static void dsa_slave_phylink_validate(struct net_device *dev,
|
|
|
|
unsigned long *supported,
|
|
|
|
struct phylink_link_state *state)
|
2014-08-28 07:04:51 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
if (!ds->ops->phylink_validate)
|
|
|
|
return;
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
ds->ops->phylink_validate(ds, dp->index, supported, state);
|
|
|
|
}
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
static int dsa_slave_phylink_mac_link_state(struct net_device *dev,
|
|
|
|
struct phylink_link_state *state)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
/* Only called for SGMII and 802.3z */
|
|
|
|
if (!ds->ops->phylink_mac_link_state)
|
|
|
|
return -EOPNOTSUPP;
|
2014-08-28 07:04:53 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
return ds->ops->phylink_mac_link_state(ds, dp->index, state);
|
2014-08-28 07:04:51 +07:00
|
|
|
}
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
static void dsa_slave_phylink_mac_config(struct net_device *dev,
|
|
|
|
unsigned int mode,
|
|
|
|
const struct phylink_link_state *state)
|
2014-08-28 07:04:54 +07:00
|
|
|
{
|
2018-05-11 03:17:36 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
if (!ds->ops->phylink_mac_config)
|
|
|
|
return;
|
2016-03-12 06:01:37 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
ds->ops->phylink_mac_config(ds, dp->index, mode, state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_phylink_mac_an_restart(struct net_device *dev)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
if (!ds->ops->phylink_mac_an_restart)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ds->ops->phylink_mac_an_restart(ds, dp->index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_phylink_mac_link_down(struct net_device *dev,
|
|
|
|
unsigned int mode,
|
|
|
|
phy_interface_t interface)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
if (!ds->ops->phylink_mac_link_down) {
|
|
|
|
if (ds->ops->adjust_link && dev->phydev)
|
|
|
|
ds->ops->adjust_link(ds, dp->index, dev->phydev);
|
|
|
|
return;
|
2016-03-12 06:01:37 +07:00
|
|
|
}
|
2014-08-28 07:04:54 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
ds->ops->phylink_mac_link_down(ds, dp->index, mode, interface);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsa_slave_phylink_mac_link_up(struct net_device *dev,
|
|
|
|
unsigned int mode,
|
|
|
|
phy_interface_t interface,
|
|
|
|
struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
if (!ds->ops->phylink_mac_link_up) {
|
|
|
|
if (ds->ops->adjust_link && dev->phydev)
|
|
|
|
ds->ops->adjust_link(ds, dp->index, dev->phydev);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
ds->ops->phylink_mac_link_up(ds, dp->index, mode, interface, phydev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct phylink_mac_ops dsa_slave_phylink_mac_ops = {
|
|
|
|
.validate = dsa_slave_phylink_validate,
|
|
|
|
.mac_link_state = dsa_slave_phylink_mac_link_state,
|
|
|
|
.mac_config = dsa_slave_phylink_mac_config,
|
|
|
|
.mac_an_restart = dsa_slave_phylink_mac_an_restart,
|
|
|
|
.mac_link_down = dsa_slave_phylink_mac_link_down,
|
|
|
|
.mac_link_up = dsa_slave_phylink_mac_link_up,
|
|
|
|
};
|
|
|
|
|
|
|
|
void dsa_port_phylink_mac_change(struct dsa_switch *ds, int port, bool up)
|
|
|
|
{
|
|
|
|
const struct dsa_port *dp = dsa_to_port(ds, port);
|
|
|
|
|
|
|
|
phylink_mac_change(dp->pl, up);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(dsa_port_phylink_mac_change);
|
|
|
|
|
|
|
|
static void dsa_slave_phylink_fixed_state(struct net_device *dev,
|
|
|
|
struct phylink_link_state *state)
|
|
|
|
{
|
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
|
|
|
|
|
|
|
/* No need to check that this operation is valid, the callback would
|
|
|
|
* not be called if it was not.
|
|
|
|
*/
|
|
|
|
ds->ops->phylink_fixed_state(ds, dp->index, state);
|
2014-08-28 07:04:54 +07:00
|
|
|
}
|
|
|
|
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
/* slave device setup *******************************************************/
|
2017-09-21 06:31:57 +07:00
|
|
|
static int dsa_slave_phy_connect(struct net_device *slave_dev, int addr)
|
2015-03-11 06:57:12 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2015-03-11 06:57:12 +07:00
|
|
|
|
2017-09-27 04:15:32 +07:00
|
|
|
slave_dev->phydev = mdiobus_get_phy(ds->slave_mii_bus, addr);
|
|
|
|
if (!slave_dev->phydev) {
|
2015-10-04 00:09:07 +07:00
|
|
|
netdev_err(slave_dev, "no phy at %d\n", addr);
|
2015-03-11 06:57:12 +07:00
|
|
|
return -ENODEV;
|
2015-10-04 00:09:07 +07:00
|
|
|
}
|
2015-03-11 06:57:12 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
return phylink_connect_phy(dp->pl, slave_dev->phydev);
|
2018-05-11 03:17:32 +07:00
|
|
|
}
|
|
|
|
|
2017-09-21 06:31:57 +07:00
|
|
|
static int dsa_slave_phy_setup(struct net_device *slave_dev)
|
2014-08-28 07:04:51 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
struct device_node *port_dn = dp->dn;
|
|
|
|
struct dsa_switch *ds = dp->ds;
|
2014-09-20 03:07:54 +07:00
|
|
|
u32 phy_flags = 0;
|
2015-02-17 12:23:51 +07:00
|
|
|
int mode, ret;
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2015-02-17 12:23:51 +07:00
|
|
|
mode = of_get_phy_mode(port_dn);
|
|
|
|
if (mode < 0)
|
|
|
|
mode = PHY_INTERFACE_MODE_NA;
|
2014-08-28 07:04:51 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
dp->pl = phylink_create(slave_dev, of_fwnode_handle(port_dn), mode,
|
|
|
|
&dsa_slave_phylink_mac_ops);
|
|
|
|
if (IS_ERR(dp->pl)) {
|
|
|
|
netdev_err(slave_dev,
|
|
|
|
"error creating PHYLINK: %ld\n", PTR_ERR(dp->pl));
|
|
|
|
return PTR_ERR(dp->pl);
|
2014-08-28 07:04:51 +07:00
|
|
|
}
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
/* Register only if the switch provides such a callback, since this
|
|
|
|
* callback takes precedence over polling the link GPIO in PHYLINK
|
|
|
|
* (see phylink_get_fixed_state).
|
|
|
|
*/
|
|
|
|
if (ds->ops->phylink_fixed_state)
|
|
|
|
phylink_fixed_state_cb(dp->pl, dsa_slave_phylink_fixed_state);
|
|
|
|
|
2016-08-23 23:38:56 +07:00
|
|
|
if (ds->ops->get_phy_flags)
|
2017-10-16 22:12:15 +07:00
|
|
|
phy_flags = ds->ops->get_phy_flags(ds, dp->index);
|
2014-09-20 03:07:54 +07:00
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
ret = phylink_of_phy_connect(dp->pl, port_dn, phy_flags);
|
|
|
|
if (ret == -ENODEV) {
|
|
|
|
/* We could not connect to a designated PHY or SFP, so use the
|
|
|
|
* switch internal MDIO bus instead
|
|
|
|
*/
|
2017-10-16 22:12:15 +07:00
|
|
|
ret = dsa_slave_phy_connect(slave_dev, dp->index);
|
2015-10-04 00:09:07 +07:00
|
|
|
if (ret) {
|
2018-05-11 03:17:36 +07:00
|
|
|
netdev_err(slave_dev,
|
|
|
|
"failed to connect to port %d: %d\n",
|
2017-10-16 22:12:15 +07:00
|
|
|
dp->index, ret);
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_destroy(dp->pl);
|
2015-03-11 06:57:12 +07:00
|
|
|
return ret;
|
2015-10-04 00:09:07 +07:00
|
|
|
}
|
2014-11-06 01:47:28 +07:00
|
|
|
}
|
2014-12-12 03:49:16 +07:00
|
|
|
|
|
|
|
return 0;
|
2014-08-28 07:04:51 +07:00
|
|
|
}
|
|
|
|
|
2015-05-06 06:09:56 +07:00
|
|
|
static struct lock_class_key dsa_slave_netdev_xmit_lock_key;
|
|
|
|
static void dsa_slave_set_lockdep_class_one(struct net_device *dev,
|
|
|
|
struct netdev_queue *txq,
|
|
|
|
void *_unused)
|
|
|
|
{
|
|
|
|
lockdep_set_class(&txq->_xmit_lock,
|
|
|
|
&dsa_slave_netdev_xmit_lock_key);
|
|
|
|
}
|
|
|
|
|
2014-09-19 07:31:22 +07:00
|
|
|
int dsa_slave_suspend(struct net_device *slave_dev)
|
|
|
|
{
|
2018-05-11 03:17:36 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
2014-09-19 07:31:22 +07:00
|
|
|
|
2018-08-01 07:12:52 +07:00
|
|
|
if (!netif_running(slave_dev))
|
|
|
|
return 0;
|
|
|
|
|
2017-01-26 00:10:41 +07:00
|
|
|
netif_device_detach(slave_dev);
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
rtnl_lock();
|
|
|
|
phylink_stop(dp->pl);
|
|
|
|
rtnl_unlock();
|
2014-09-19 07:31:22 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dsa_slave_resume(struct net_device *slave_dev)
|
|
|
|
{
|
2018-05-11 03:17:36 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
|
|
|
|
2018-08-01 07:12:52 +07:00
|
|
|
if (!netif_running(slave_dev))
|
|
|
|
return 0;
|
|
|
|
|
2014-09-19 07:31:22 +07:00
|
|
|
netif_device_attach(slave_dev);
|
|
|
|
|
2018-05-11 03:17:36 +07:00
|
|
|
rtnl_lock();
|
|
|
|
phylink_start(dp->pl);
|
|
|
|
rtnl_unlock();
|
2014-09-19 07:31:22 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-16 22:12:14 +07:00
|
|
|
static void dsa_slave_notify(struct net_device *dev, unsigned long val)
|
|
|
|
{
|
2017-10-16 22:12:16 +07:00
|
|
|
struct net_device *master = dsa_slave_to_master(dev);
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-10-16 22:12:14 +07:00
|
|
|
struct dsa_notifier_register_info rinfo = {
|
|
|
|
.switch_number = dp->ds->index,
|
|
|
|
.port_number = dp->index,
|
|
|
|
.master = master,
|
|
|
|
.info.dev = dev,
|
|
|
|
};
|
|
|
|
|
|
|
|
call_dsa_notifiers(val, dev, &rinfo.info);
|
|
|
|
}
|
|
|
|
|
2017-10-28 02:55:19 +07:00
|
|
|
int dsa_slave_create(struct dsa_port *port)
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
{
|
2017-11-07 04:11:43 +07:00
|
|
|
const struct dsa_port *cpu_dp = port->cpu_dp;
|
2017-10-16 22:12:18 +07:00
|
|
|
struct net_device *master = cpu_dp->master;
|
2017-08-06 03:20:19 +07:00
|
|
|
struct dsa_switch *ds = port->ds;
|
2017-10-28 02:55:19 +07:00
|
|
|
const char *name = port->name;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
struct net_device *slave_dev;
|
|
|
|
struct dsa_slave_priv *p;
|
|
|
|
int ret;
|
|
|
|
|
2017-09-04 10:27:00 +07:00
|
|
|
if (!ds->num_tx_queues)
|
|
|
|
ds->num_tx_queues = 1;
|
|
|
|
|
|
|
|
slave_dev = alloc_netdev_mqs(sizeof(struct dsa_slave_priv), name,
|
|
|
|
NET_NAME_UNKNOWN, ether_setup,
|
|
|
|
ds->num_tx_queues, 1);
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
if (slave_dev == NULL)
|
2015-02-25 04:15:32 +07:00
|
|
|
return -ENOMEM;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
2019-02-21 05:35:39 +07:00
|
|
|
slave_dev->features = master->vlan_features | NETIF_F_HW_TC |
|
|
|
|
NETIF_F_HW_VLAN_CTAG_FILTER;
|
2017-01-31 03:41:40 +07:00
|
|
|
slave_dev->hw_features |= NETIF_F_HW_TC;
|
2014-05-11 07:12:32 +07:00
|
|
|
slave_dev->ethtool_ops = &dsa_slave_ethtool_ops;
|
2013-08-30 23:08:46 +07:00
|
|
|
eth_hw_addr_inherit(slave_dev, master);
|
2015-08-18 15:30:41 +07:00
|
|
|
slave_dev->priv_flags |= IFF_NO_QUEUE;
|
2014-08-28 07:04:46 +07:00
|
|
|
slave_dev->netdev_ops = &dsa_slave_netdev_ops;
|
2016-10-21 10:25:27 +07:00
|
|
|
slave_dev->min_mtu = 0;
|
|
|
|
slave_dev->max_mtu = ETH_MAX_MTU;
|
2015-09-24 08:19:58 +07:00
|
|
|
SET_NETDEV_DEVTYPE(slave_dev, &dsa_type);
|
2009-01-07 07:45:26 +07:00
|
|
|
|
2015-05-06 06:09:56 +07:00
|
|
|
netdev_for_each_tx_queue(slave_dev, dsa_slave_set_lockdep_class_one,
|
|
|
|
NULL);
|
|
|
|
|
2017-08-06 03:20:19 +07:00
|
|
|
SET_NETDEV_DEV(slave_dev, port->ds->dev);
|
|
|
|
slave_dev->dev.of_node = port->dn;
|
2014-09-16 00:00:19 +07:00
|
|
|
slave_dev->vlan_features = master->vlan_features;
|
|
|
|
|
|
|
|
p = netdev_priv(slave_dev);
|
2017-08-04 11:33:27 +07:00
|
|
|
p->stats64 = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats);
|
|
|
|
if (!p->stats64) {
|
|
|
|
free_netdev(slave_dev);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2017-08-06 03:20:19 +07:00
|
|
|
p->dp = port;
|
2017-01-31 03:41:40 +07:00
|
|
|
INIT_LIST_HEAD(&p->mall_tc_list);
|
2017-09-30 04:19:18 +07:00
|
|
|
p->xmit = cpu_dp->tag_ops->xmit;
|
2017-10-16 22:12:18 +07:00
|
|
|
port->slave = slave_dev;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
|
|
|
|
netif_carrier_off(slave_dev);
|
|
|
|
|
2017-09-21 06:31:57 +07:00
|
|
|
ret = dsa_slave_phy_setup(slave_dev);
|
2016-01-07 02:11:20 +07:00
|
|
|
if (ret) {
|
|
|
|
netdev_err(master, "error %d setting up slave phy\n", ret);
|
2017-09-26 05:55:53 +07:00
|
|
|
goto out_free;
|
|
|
|
}
|
|
|
|
|
2017-10-16 22:12:14 +07:00
|
|
|
dsa_slave_notify(slave_dev, DSA_PORT_REGISTER);
|
2017-10-12 00:57:48 +07:00
|
|
|
|
2017-09-26 05:55:53 +07:00
|
|
|
ret = register_netdev(slave_dev);
|
|
|
|
if (ret) {
|
|
|
|
netdev_err(master, "error %d registering interface %s\n",
|
|
|
|
ret, slave_dev->name);
|
|
|
|
goto out_phy;
|
2016-01-07 02:11:20 +07:00
|
|
|
}
|
|
|
|
|
2015-02-25 04:15:32 +07:00
|
|
|
return 0;
|
2017-09-26 05:55:53 +07:00
|
|
|
|
|
|
|
out_phy:
|
2018-05-11 03:17:36 +07:00
|
|
|
rtnl_lock();
|
|
|
|
phylink_disconnect_phy(p->dp->pl);
|
|
|
|
rtnl_unlock();
|
|
|
|
phylink_destroy(p->dp->pl);
|
2017-09-26 05:55:53 +07:00
|
|
|
out_free:
|
|
|
|
free_percpu(p->stats64);
|
|
|
|
free_netdev(slave_dev);
|
2017-10-16 22:12:18 +07:00
|
|
|
port->slave = NULL;
|
2017-09-26 05:55:53 +07:00
|
|
|
return ret;
|
net: Distributed Switch Architecture protocol support
Distributed Switch Architecture is a protocol for managing hardware
switch chips. It consists of a set of MII management registers and
commands to configure the switch, and an ethernet header format to
signal which of the ports of the switch a packet was received from
or is intended to be sent to.
The switches that this driver supports are typically embedded in
access points and routers, and a typical setup with a DSA switch
looks something like this:
+-----------+ +-----------+
| | RGMII | |
| +-------+ +------ 1000baseT MDI ("WAN")
| | | 6-port +------ 1000baseT MDI ("LAN1")
| CPU | | ethernet +------ 1000baseT MDI ("LAN2")
| |MIImgmt| switch +------ 1000baseT MDI ("LAN3")
| +-------+ w/5 PHYs +------ 1000baseT MDI ("LAN4")
| | | |
+-----------+ +-----------+
The switch driver presents each port on the switch as a separate
network interface to Linux, polls the switch to maintain software
link state of those ports, forwards MII management interface
accesses to those network interfaces (e.g. as done by ethtool) to
the switch, and exposes the switch's hardware statistics counters
via the appropriate Linux kernel interfaces.
This initial patch supports the MII management interface register
layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
supports the "Ethertype DSA" packet tagging format.
(There is no officially registered ethertype for the Ethertype DSA
packet format, so we just grab a random one. The ethertype to use
is programmed into the switch, and the switch driver uses the value
of ETH_P_EDSA for this, so this define can be changed at any time in
the future if the one we chose is allocated to another protocol or
if Ethertype DSA gets its own officially registered ethertype, and
everything will continue to work.)
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Nicolas Pitre <nico@marvell.com>
Tested-by: Byron Bradley <byron.bbradley@gmail.com>
Tested-by: Tim Ellis <tim.ellis@mac.com>
Tested-by: Peter van Valderen <linux@ddcrew.com>
Tested-by: Dirk Teurlings <dirk@upexia.nl>
Signed-off-by: David S. Miller <davem@davemloft.net>
2008-10-07 20:44:02 +07:00
|
|
|
}
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2015-12-07 19:57:35 +07:00
|
|
|
void dsa_slave_destroy(struct net_device *slave_dev)
|
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(slave_dev);
|
2015-12-07 19:57:35 +07:00
|
|
|
struct dsa_slave_priv *p = netdev_priv(slave_dev);
|
|
|
|
|
|
|
|
netif_carrier_off(slave_dev);
|
2018-05-11 03:17:36 +07:00
|
|
|
rtnl_lock();
|
|
|
|
phylink_disconnect_phy(dp->pl);
|
|
|
|
rtnl_unlock();
|
2016-11-29 01:25:09 +07:00
|
|
|
|
2017-10-16 22:12:14 +07:00
|
|
|
dsa_slave_notify(slave_dev, DSA_PORT_UNREGISTER);
|
2015-12-07 19:57:35 +07:00
|
|
|
unregister_netdev(slave_dev);
|
2018-05-11 03:17:36 +07:00
|
|
|
phylink_destroy(dp->pl);
|
2017-08-04 11:33:27 +07:00
|
|
|
free_percpu(p->stats64);
|
2015-12-07 19:57:35 +07:00
|
|
|
free_netdev(slave_dev);
|
|
|
|
}
|
|
|
|
|
2015-02-25 04:15:33 +07:00
|
|
|
static bool dsa_slave_dev_check(struct net_device *dev)
|
|
|
|
{
|
|
|
|
return dev->netdev_ops == &dsa_slave_netdev_ops;
|
|
|
|
}
|
|
|
|
|
2017-02-04 01:20:17 +07:00
|
|
|
static int dsa_slave_changeupper(struct net_device *dev,
|
|
|
|
struct netdev_notifier_changeupper_info *info)
|
2015-02-25 04:15:33 +07:00
|
|
|
{
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-02-04 01:20:17 +07:00
|
|
|
int err = NOTIFY_DONE;
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2017-02-04 01:20:17 +07:00
|
|
|
if (netif_is_bridge_master(info->upper_dev)) {
|
|
|
|
if (info->linking) {
|
2017-05-20 04:00:38 +07:00
|
|
|
err = dsa_port_bridge_join(dp, info->upper_dev);
|
2017-02-04 01:20:17 +07:00
|
|
|
err = notifier_from_errno(err);
|
|
|
|
} else {
|
2017-05-20 04:00:38 +07:00
|
|
|
dsa_port_bridge_leave(dp, info->upper_dev);
|
2017-02-04 01:20:17 +07:00
|
|
|
err = NOTIFY_OK;
|
2016-03-14 03:21:34 +07:00
|
|
|
}
|
|
|
|
}
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2017-02-04 01:20:17 +07:00
|
|
|
return err;
|
2016-03-14 03:21:34 +07:00
|
|
|
}
|
2015-02-25 04:15:33 +07:00
|
|
|
|
2019-02-21 05:35:38 +07:00
|
|
|
static int dsa_slave_upper_vlan_check(struct net_device *dev,
|
|
|
|
struct netdev_notifier_changeupper_info *
|
|
|
|
info)
|
|
|
|
{
|
|
|
|
struct netlink_ext_ack *ext_ack;
|
|
|
|
struct net_device *slave;
|
|
|
|
struct dsa_port *dp;
|
|
|
|
|
|
|
|
ext_ack = netdev_notifier_info_to_extack(&info->info);
|
|
|
|
|
|
|
|
if (!is_vlan_dev(dev))
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
slave = vlan_dev_real_dev(dev);
|
|
|
|
if (!dsa_slave_dev_check(slave))
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
dp = dsa_slave_to_port(slave);
|
|
|
|
if (!dp->bridge_dev)
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
/* Deny enslaving a VLAN device into a VLAN-aware bridge */
|
|
|
|
if (br_vlan_enabled(dp->bridge_dev) &&
|
|
|
|
netif_is_bridge_master(info->upper_dev) && info->linking) {
|
|
|
|
NL_SET_ERR_MSG_MOD(ext_ack,
|
|
|
|
"Cannot enslave VLAN device into VLAN aware bridge");
|
|
|
|
return notifier_from_errno(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
}
|
|
|
|
|
2017-02-04 01:20:16 +07:00
|
|
|
static int dsa_slave_netdevice_event(struct notifier_block *nb,
|
|
|
|
unsigned long event, void *ptr)
|
2016-03-14 03:21:34 +07:00
|
|
|
{
|
|
|
|
struct net_device *dev = netdev_notifier_info_to_dev(ptr);
|
|
|
|
|
2019-02-21 05:35:38 +07:00
|
|
|
if (event == NETDEV_CHANGEUPPER) {
|
|
|
|
if (!dsa_slave_dev_check(dev))
|
|
|
|
return dsa_slave_upper_vlan_check(dev, ptr);
|
2017-02-04 01:20:17 +07:00
|
|
|
|
|
|
|
return dsa_slave_changeupper(dev, ptr);
|
2019-02-21 05:35:38 +07:00
|
|
|
}
|
2015-02-25 04:15:33 +07:00
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
}
|
2017-02-04 01:20:16 +07:00
|
|
|
|
2019-02-28 02:44:27 +07:00
|
|
|
static int
|
|
|
|
dsa_slave_switchdev_port_attr_set_event(struct net_device *netdev,
|
|
|
|
struct switchdev_notifier_port_attr_info *port_attr_info)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = dsa_slave_port_attr_set(netdev, port_attr_info->attr,
|
|
|
|
port_attr_info->trans);
|
|
|
|
|
|
|
|
port_attr_info->handled = true;
|
|
|
|
return notifier_from_errno(err);
|
|
|
|
}
|
|
|
|
|
2017-08-06 20:15:42 +07:00
|
|
|
struct dsa_switchdev_event_work {
|
|
|
|
struct work_struct work;
|
|
|
|
struct switchdev_notifier_fdb_info fdb_info;
|
|
|
|
struct net_device *dev;
|
|
|
|
unsigned long event;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void dsa_slave_switchdev_event_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct dsa_switchdev_event_work *switchdev_work =
|
|
|
|
container_of(work, struct dsa_switchdev_event_work, work);
|
|
|
|
struct net_device *dev = switchdev_work->dev;
|
|
|
|
struct switchdev_notifier_fdb_info *fdb_info;
|
2017-10-16 22:12:15 +07:00
|
|
|
struct dsa_port *dp = dsa_slave_to_port(dev);
|
2017-08-06 20:15:42 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
rtnl_lock();
|
|
|
|
switch (switchdev_work->event) {
|
|
|
|
case SWITCHDEV_FDB_ADD_TO_DEVICE:
|
|
|
|
fdb_info = &switchdev_work->fdb_info;
|
2018-05-09 10:03:12 +07:00
|
|
|
if (!fdb_info->added_by_user)
|
|
|
|
break;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
err = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid);
|
2017-08-06 20:15:42 +07:00
|
|
|
if (err) {
|
|
|
|
netdev_dbg(dev, "fdb add failed err=%d\n", err);
|
|
|
|
break;
|
|
|
|
}
|
2018-10-17 15:53:29 +07:00
|
|
|
fdb_info->offloaded = true;
|
2017-08-06 20:15:42 +07:00
|
|
|
call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, dev,
|
2019-01-17 06:06:56 +07:00
|
|
|
&fdb_info->info, NULL);
|
2017-08-06 20:15:42 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SWITCHDEV_FDB_DEL_TO_DEVICE:
|
|
|
|
fdb_info = &switchdev_work->fdb_info;
|
2018-05-09 10:03:12 +07:00
|
|
|
if (!fdb_info->added_by_user)
|
|
|
|
break;
|
|
|
|
|
2017-10-16 22:12:15 +07:00
|
|
|
err = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid);
|
2017-08-06 20:15:42 +07:00
|
|
|
if (err) {
|
|
|
|
netdev_dbg(dev, "fdb del failed err=%d\n", err);
|
|
|
|
dev_close(dev);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
rtnl_unlock();
|
|
|
|
|
|
|
|
kfree(switchdev_work->fdb_info.addr);
|
|
|
|
kfree(switchdev_work);
|
|
|
|
dev_put(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
dsa_slave_switchdev_fdb_work_init(struct dsa_switchdev_event_work *
|
|
|
|
switchdev_work,
|
|
|
|
const struct switchdev_notifier_fdb_info *
|
|
|
|
fdb_info)
|
|
|
|
{
|
|
|
|
memcpy(&switchdev_work->fdb_info, fdb_info,
|
|
|
|
sizeof(switchdev_work->fdb_info));
|
|
|
|
switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC);
|
|
|
|
if (!switchdev_work->fdb_info.addr)
|
|
|
|
return -ENOMEM;
|
|
|
|
ether_addr_copy((u8 *)switchdev_work->fdb_info.addr,
|
|
|
|
fdb_info->addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called under rcu_read_lock() */
|
|
|
|
static int dsa_slave_switchdev_event(struct notifier_block *unused,
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
{
|
|
|
|
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
|
|
|
|
struct dsa_switchdev_event_work *switchdev_work;
|
|
|
|
|
|
|
|
if (!dsa_slave_dev_check(dev))
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
2019-02-28 02:44:27 +07:00
|
|
|
if (event == SWITCHDEV_PORT_ATTR_SET)
|
|
|
|
return dsa_slave_switchdev_port_attr_set_event(dev, ptr);
|
|
|
|
|
2017-08-06 20:15:42 +07:00
|
|
|
switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);
|
|
|
|
if (!switchdev_work)
|
|
|
|
return NOTIFY_BAD;
|
|
|
|
|
|
|
|
INIT_WORK(&switchdev_work->work,
|
|
|
|
dsa_slave_switchdev_event_work);
|
|
|
|
switchdev_work->dev = dev;
|
|
|
|
switchdev_work->event = event;
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
case SWITCHDEV_FDB_ADD_TO_DEVICE: /* fall through */
|
|
|
|
case SWITCHDEV_FDB_DEL_TO_DEVICE:
|
2018-05-09 10:03:12 +07:00
|
|
|
if (dsa_slave_switchdev_fdb_work_init(switchdev_work, ptr))
|
2017-08-06 20:15:42 +07:00
|
|
|
goto err_fdb_work_init;
|
|
|
|
dev_hold(dev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
kfree(switchdev_work);
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
dsa_schedule_work(&switchdev_work->work);
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
|
|
err_fdb_work_init:
|
|
|
|
kfree(switchdev_work);
|
|
|
|
return NOTIFY_BAD;
|
|
|
|
}
|
|
|
|
|
2018-11-23 06:29:05 +07:00
|
|
|
static int
|
|
|
|
dsa_slave_switchdev_port_obj_event(unsigned long event,
|
|
|
|
struct net_device *netdev,
|
|
|
|
struct switchdev_notifier_port_obj_info *port_obj_info)
|
|
|
|
{
|
|
|
|
int err = -EOPNOTSUPP;
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
case SWITCHDEV_PORT_OBJ_ADD:
|
|
|
|
err = dsa_slave_port_obj_add(netdev, port_obj_info->obj,
|
|
|
|
port_obj_info->trans);
|
|
|
|
break;
|
|
|
|
case SWITCHDEV_PORT_OBJ_DEL:
|
|
|
|
err = dsa_slave_port_obj_del(netdev, port_obj_info->obj);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
port_obj_info->handled = true;
|
|
|
|
return notifier_from_errno(err);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dsa_slave_switchdev_blocking_event(struct notifier_block *unused,
|
|
|
|
unsigned long event, void *ptr)
|
|
|
|
{
|
|
|
|
struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
|
|
|
|
|
|
|
|
if (!dsa_slave_dev_check(dev))
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
case SWITCHDEV_PORT_OBJ_ADD: /* fall through */
|
|
|
|
case SWITCHDEV_PORT_OBJ_DEL:
|
|
|
|
return dsa_slave_switchdev_port_obj_event(event, dev, ptr);
|
2019-02-28 02:44:27 +07:00
|
|
|
case SWITCHDEV_PORT_ATTR_SET:
|
|
|
|
return dsa_slave_switchdev_port_attr_set_event(dev, ptr);
|
2018-11-23 06:29:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
}
|
|
|
|
|
2017-02-04 01:20:16 +07:00
|
|
|
static struct notifier_block dsa_slave_nb __read_mostly = {
|
2017-08-06 20:15:42 +07:00
|
|
|
.notifier_call = dsa_slave_netdevice_event,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct notifier_block dsa_slave_switchdev_notifier = {
|
|
|
|
.notifier_call = dsa_slave_switchdev_event,
|
2017-02-04 01:20:16 +07:00
|
|
|
};
|
|
|
|
|
2018-11-23 06:29:05 +07:00
|
|
|
static struct notifier_block dsa_slave_switchdev_blocking_notifier = {
|
|
|
|
.notifier_call = dsa_slave_switchdev_blocking_event,
|
|
|
|
};
|
|
|
|
|
2017-02-04 01:20:16 +07:00
|
|
|
int dsa_slave_register_notifier(void)
|
|
|
|
{
|
2018-11-23 06:29:05 +07:00
|
|
|
struct notifier_block *nb;
|
2017-08-06 20:15:42 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
err = register_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = register_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
|
|
|
if (err)
|
|
|
|
goto err_switchdev_nb;
|
|
|
|
|
2018-11-23 06:29:05 +07:00
|
|
|
nb = &dsa_slave_switchdev_blocking_notifier;
|
|
|
|
err = register_switchdev_blocking_notifier(nb);
|
|
|
|
if (err)
|
|
|
|
goto err_switchdev_blocking_nb;
|
|
|
|
|
2017-08-06 20:15:42 +07:00
|
|
|
return 0;
|
|
|
|
|
2018-11-23 06:29:05 +07:00
|
|
|
err_switchdev_blocking_nb:
|
|
|
|
unregister_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
2017-08-06 20:15:42 +07:00
|
|
|
err_switchdev_nb:
|
|
|
|
unregister_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
return err;
|
2017-02-04 01:20:16 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void dsa_slave_unregister_notifier(void)
|
|
|
|
{
|
2018-11-23 06:29:05 +07:00
|
|
|
struct notifier_block *nb;
|
2017-02-04 01:20:16 +07:00
|
|
|
int err;
|
|
|
|
|
2018-11-23 06:29:05 +07:00
|
|
|
nb = &dsa_slave_switchdev_blocking_notifier;
|
|
|
|
err = unregister_switchdev_blocking_notifier(nb);
|
|
|
|
if (err)
|
|
|
|
pr_err("DSA: failed to unregister switchdev blocking notifier (%d)\n", err);
|
|
|
|
|
2017-08-06 20:15:42 +07:00
|
|
|
err = unregister_switchdev_notifier(&dsa_slave_switchdev_notifier);
|
|
|
|
if (err)
|
|
|
|
pr_err("DSA: failed to unregister switchdev notifier (%d)\n", err);
|
|
|
|
|
2017-02-04 01:20:16 +07:00
|
|
|
err = unregister_netdevice_notifier(&dsa_slave_nb);
|
|
|
|
if (err)
|
|
|
|
pr_err("DSA: failed to unregister slave notifier (%d)\n", err);
|
|
|
|
}
|