2019-05-27 13:55:08 +07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
2011-10-17 07:42:17 +07:00
|
|
|
/*
|
|
|
|
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
|
|
|
* Copyright 2011 Linaro Ltd.
|
|
|
|
*/
|
|
|
|
|
2014-05-20 14:34:06 +07:00
|
|
|
#include <linux/io.h>
|
2011-10-17 07:42:17 +07:00
|
|
|
#include <linux/irq.h>
|
2018-07-10 01:19:15 +07:00
|
|
|
#include <linux/of_address.h>
|
2011-10-17 07:42:17 +07:00
|
|
|
#include <linux/of_irq.h>
|
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <asm/mach/arch.h>
|
|
|
|
#include <asm/mach/time.h>
|
|
|
|
|
2012-09-13 20:01:00 +07:00
|
|
|
#include "common.h"
|
2014-05-20 14:34:06 +07:00
|
|
|
#include "hardware.h"
|
2012-09-13 20:01:00 +07:00
|
|
|
|
2014-05-20 14:34:06 +07:00
|
|
|
static void __init imx51_init_early(void)
|
|
|
|
{
|
|
|
|
mxc_set_cpu_type(MXC_CPU_MX51);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
|
|
|
|
* the Freescale marketing division. However this did not remove the
|
|
|
|
* hardware from the chip which still needs to be configured for proper
|
|
|
|
* IPU support.
|
|
|
|
*/
|
|
|
|
#define MX51_MIPI_HSC_BASE 0x83fdc000
|
|
|
|
static void __init imx51_ipu_mipi_setup(void)
|
|
|
|
{
|
|
|
|
void __iomem *hsc_addr;
|
|
|
|
|
|
|
|
hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
|
|
|
|
WARN_ON(!hsc_addr);
|
|
|
|
|
|
|
|
/* setup MIPI module to legacy mode */
|
2016-01-27 23:59:35 +07:00
|
|
|
imx_writel(0xf00, hsc_addr);
|
2014-05-20 14:34:06 +07:00
|
|
|
|
|
|
|
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
|
2016-01-27 23:59:35 +07:00
|
|
|
imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800);
|
2014-05-20 14:34:06 +07:00
|
|
|
|
|
|
|
iounmap(hsc_addr);
|
|
|
|
}
|
|
|
|
|
2018-07-10 01:19:15 +07:00
|
|
|
static void __init imx51_m4if_setup(void)
|
|
|
|
{
|
|
|
|
void __iomem *m4if_base;
|
|
|
|
struct device_node *np;
|
|
|
|
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if");
|
|
|
|
if (!np)
|
|
|
|
return;
|
|
|
|
|
|
|
|
m4if_base = of_iomap(np, 0);
|
2019-03-01 15:56:46 +07:00
|
|
|
of_node_put(np);
|
2018-07-10 01:19:15 +07:00
|
|
|
if (!m4if_base) {
|
|
|
|
pr_err("Unable to map M4IF registers\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure VPU and IPU with higher priorities
|
|
|
|
* in order to avoid artifacts during video playback
|
|
|
|
*/
|
|
|
|
writel_relaxed(0x00000203, m4if_base + 0x40);
|
|
|
|
writel_relaxed(0x00000000, m4if_base + 0x44);
|
|
|
|
writel_relaxed(0x00120125, m4if_base + 0x9c);
|
|
|
|
writel_relaxed(0x001901A3, m4if_base + 0x48);
|
|
|
|
iounmap(m4if_base);
|
|
|
|
}
|
|
|
|
|
2011-10-17 07:42:17 +07:00
|
|
|
static void __init imx51_dt_init(void)
|
|
|
|
{
|
2014-05-20 14:34:06 +07:00
|
|
|
imx51_ipu_mipi_setup();
|
|
|
|
imx_src_init();
|
2018-07-10 01:19:15 +07:00
|
|
|
imx51_m4if_setup();
|
2018-07-10 23:31:48 +07:00
|
|
|
imx5_pmu_init();
|
2016-06-25 12:26:15 +07:00
|
|
|
imx_aips_allow_unprivileged_access("fsl,imx51-aipstz");
|
2011-10-17 07:42:17 +07:00
|
|
|
}
|
|
|
|
|
2014-05-20 14:34:06 +07:00
|
|
|
static void __init imx51_init_late(void)
|
|
|
|
{
|
|
|
|
mx51_neon_fixup();
|
|
|
|
imx51_pm_init();
|
|
|
|
}
|
|
|
|
|
2014-07-01 15:03:00 +07:00
|
|
|
static const char * const imx51_dt_board_compat[] __initconst = {
|
2012-02-17 18:07:00 +07:00
|
|
|
"fsl,imx51",
|
2011-10-17 07:42:17 +07:00
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
|
|
|
|
.init_early = imx51_init_early,
|
|
|
|
.init_machine = imx51_dt_init,
|
2012-04-26 10:42:34 +07:00
|
|
|
.init_late = imx51_init_late,
|
2011-10-17 07:42:17 +07:00
|
|
|
.dt_compat = imx51_dt_board_compat,
|
|
|
|
MACHINE_END
|