mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
176 lines
4.0 KiB
ArmAsm
176 lines
4.0 KiB
ArmAsm
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/*
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* Copyright (C) 2009 Wind River Systems Inc
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* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
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* Copyright (C) 2004 Microtronix Datacom Ltd
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* Copyright (C) 2001 Vic Phillips, Microtronix Datacom Ltd.
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*
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* Based on head.S for Altera's Excalibur development board with nios processor
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*
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* Based on the following from the Excalibur sdk distribution:
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* NA_MemoryMap.s, NR_JumpToStart.s, NR_Setup.s, NR_CWPManager.s
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm-macros.h>
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/*
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* ZERO_PAGE is a special page that is used for zero-initialized
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* data and COW.
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*/
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.data
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.global empty_zero_page
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.align 12
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empty_zero_page:
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.space PAGE_SIZE
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/*
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* This global variable is used as an extension to the nios'
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* STATUS register to emulate a user/supervisor mode.
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*/
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.data
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.align 2
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.set noat
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.global _current_thread
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_current_thread:
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.long 0
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/*
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* Input(s): passed from u-boot
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* r4 - Optional pointer to a board information structure.
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* r5 - Optional pointer to the physical starting address of the init RAM
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* disk.
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* r6 - Optional pointer to the physical ending address of the init RAM
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* disk.
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* r7 - Optional pointer to the physical starting address of any kernel
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* command-line parameters.
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*/
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/*
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* First executable code - detected and jumped to by the ROM bootstrap
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* if the code resides in flash (looks for "Nios" at offset 0x0c from
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* the potential executable image).
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*/
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__HEAD
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ENTRY(_start)
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wrctl status, r0 /* Disable interrupts */
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/* Initialize all cache lines within the instruction cache */
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movia r1, NIOS2_ICACHE_SIZE
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movui r2, NIOS2_ICACHE_LINE_SIZE
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icache_init:
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initi r1
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sub r1, r1, r2
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bgt r1, r0, icache_init
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br 1f
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/*
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* This is the default location for the exception handler. Code in jump
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* to our handler
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*/
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ENTRY(exception_handler_hook)
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movia r24, inthandler
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jmp r24
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ENTRY(fast_handler)
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nextpc et
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helper:
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stw r3, r3save - helper(et)
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rdctl r3 , pteaddr
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srli r3, r3, 12
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slli r3, r3, 2
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movia et, pgd_current
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ldw et, 0(et)
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add r3, et, r3
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ldw et, 0(r3)
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rdctl r3, pteaddr
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andi r3, r3, 0xfff
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add et, r3, et
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ldw et, 0(et)
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wrctl tlbacc, et
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nextpc et
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helper2:
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ldw r3, r3save - helper2(et)
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subi ea, ea, 4
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eret
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r3save:
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.word 0x0
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ENTRY(fast_handler_end)
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1:
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/*
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* After the instruction cache is initialized, the data cache must
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* also be initialized.
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*/
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movia r1, NIOS2_DCACHE_SIZE
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movui r2, NIOS2_DCACHE_LINE_SIZE
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dcache_init:
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initd 0(r1)
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sub r1, r1, r2
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bgt r1, r0, dcache_init
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nextpc r1 /* Find out where we are */
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chkadr:
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movia r2, chkadr
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beq r1, r2,finish_move /* We are running in RAM done */
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addi r1, r1,(_start - chkadr) /* Source */
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movia r2, _start /* Destination */
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movia r3, __bss_start /* End of copy */
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loop_move: /* r1: src, r2: dest, r3: last dest */
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ldw r8, 0(r1) /* load a word from [r1] */
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stw r8, 0(r2) /* store a word to dest [r2] */
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flushd 0(r2) /* Flush cache for safety */
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addi r1, r1, 4 /* inc the src addr */
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addi r2, r2, 4 /* inc the dest addr */
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blt r2, r3, loop_move
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movia r1, finish_move /* VMA(_start)->l1 */
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jmp r1 /* jmp to _start */
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finish_move:
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/* Mask off all possible interrupts */
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wrctl ienable, r0
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/* Clear .bss */
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movia r2, __bss_start
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movia r1, __bss_stop
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1:
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stb r0, 0(r2)
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addi r2, r2, 1
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bne r1, r2, 1b
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movia r1, init_thread_union /* set stack at top of the task union */
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addi sp, r1, THREAD_SIZE
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movia r2, _current_thread /* Remember current thread */
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stw r1, 0(r2)
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movia r1, nios2_boot_init /* save args r4-r7 passed from u-boot */
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callr r1
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movia r1, start_kernel /* call start_kernel as a subroutine */
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callr r1
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/* If we return from start_kernel, break to the oci debugger and
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* buggered we are.
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*/
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break
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/* End of startup code */
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.set at
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