AuxXxilium/linux_dsm_epyc7002
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linux_dsm_epyc7002/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h

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clk: sunxi-ng: Add driver for A83T CCU The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-19 14:06:09 +07:00
/*
* Copyright 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CCU_SUN8I_A83T_H_
#define _CCU_SUN8I_A83T_H_
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#define CLK_PLL_C0CPUX 0
#define CLK_PLL_C1CPUX 1
#define CLK_PLL_AUDIO 2
#define CLK_PLL_VIDEO0 3
#define CLK_PLL_VE 4
#define CLK_PLL_DDR 5
/* pll-periph is exported to the PRCM block */
#define CLK_PLL_GPU 7
#define CLK_PLL_HSIC 8
/* pll-de is exported for the display engine */
#define CLK_PLL_VIDEO1 10
/* The CPUX clocks are exported */
#define CLK_AXI0 13
#define CLK_AXI1 14
#define CLK_AHB1 15
#define CLK_AHB2 16
#define CLK_APB1 17
#define CLK_APB2 18
/* bus gates exported */
#define CLK_CCI400 58
/* module and usb clocks exported */
#define CLK_DRAM 82
/* dram gates and more module clocks exported */
#define CLK_MBUS 95
/* more module clocks exported */
#define CLK_NUMBER (CLK_GPU_HYD + 1)
#endif /* _CCU_SUN8I_A83T_H_ */
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