2005-04-17 05:20:36 +07:00
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/*
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* DTC controller, taken from T128 driver by...
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 440-4894
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*/
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#ifndef DTC3280_H
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#define DTC3280_H
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#define NCR5380_implementation_fields \
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void __iomem *base
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2016-01-03 12:05:06 +07:00
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#define DTC_address(reg) \
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(((struct NCR5380_hostdata *)shost_priv(instance))->base + DTC_5380_OFFSET + reg)
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2005-04-17 05:20:36 +07:00
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#define NCR5380_read(reg) (readb(DTC_address(reg)))
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#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
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2016-01-03 12:05:25 +07:00
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#define NCR5380_dma_xfer_len(instance, cmd, phase) \
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dtc_dma_xfer_len(cmd)
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2016-03-23 17:10:17 +07:00
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#define NCR5380_dma_recv_setup dtc_pread
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#define NCR5380_dma_send_setup dtc_pwrite
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2016-03-23 17:10:19 +07:00
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#define NCR5380_dma_residual(instance) (0)
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2016-01-03 12:05:25 +07:00
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2005-04-17 05:20:36 +07:00
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#define NCR5380_intr dtc_intr
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#define NCR5380_queue_command dtc_queue_command
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#define NCR5380_abort dtc_abort
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#define NCR5380_bus_reset dtc_bus_reset
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2014-11-12 12:11:58 +07:00
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#define NCR5380_info dtc_info
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2005-04-17 05:20:36 +07:00
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2016-03-23 17:10:16 +07:00
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#define NCR5380_io_delay(x) udelay(x)
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2005-04-17 05:20:36 +07:00
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/* 15 12 11 10
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1001 1100 0000 0000 */
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#define DTC_IRQS 0x9c00
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#endif /* DTC3280_H */
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