2012-06-22 16:40:48 +07:00
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/*
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* Device Tree Source for AM33XX SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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2018-09-25 06:20:54 +07:00
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#include <dt-bindings/bus/ti-sysc.h>
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2013-06-03 21:12:23 +07:00
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#include <dt-bindings/gpio/gpio.h>
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2013-06-03 21:12:25 +07:00
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#include <dt-bindings/pinctrl/am33xx.h>
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2017-12-08 22:17:30 +07:00
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#include <dt-bindings/clock/am3.h>
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2013-06-03 21:12:23 +07:00
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2012-06-22 16:40:48 +07:00
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/ {
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compatible = "ti,am33xx";
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2012-10-24 15:47:52 +07:00
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interrupt-parent = <&intc>;
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2016-08-31 17:35:21 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2016-12-19 21:44:37 +07:00
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chosen { };
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2012-06-22 16:40:48 +07:00
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aliases {
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2013-10-17 03:21:04 +07:00
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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2013-03-28 13:06:05 +07:00
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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2018-06-11 21:45:53 +07:00
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d-can0 = &dcan0;
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d-can1 = &dcan1;
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2013-07-05 19:51:33 +07:00
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usb0 = &usb0;
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usb1 = &usb1;
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phy0 = &usb0_phy;
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phy1 = &usb1_phy;
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2013-10-03 00:58:33 +07:00
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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2017-09-11 13:30:16 +07:00
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spi0 = &spi0;
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spi1 = &spi1;
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2012-06-22 16:40:48 +07:00
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};
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cpus {
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2013-04-19 00:35:59 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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2012-06-22 16:40:48 +07:00
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cpu@0 {
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compatible = "arm,cortex-a8";
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2013-04-19 00:35:59 +07:00
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device_type = "cpu";
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reg = <0>;
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2012-08-31 16:37:20 +07:00
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2017-03-06 22:23:38 +07:00
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operating-points-v2 = <&cpu0_opp_table>;
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2014-01-30 01:19:17 +07:00
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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2012-08-31 16:37:20 +07:00
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clock-latency = <300000>; /* From omap-cpufreq driver */
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2012-06-22 16:40:48 +07:00
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};
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};
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2017-03-06 22:23:38 +07:00
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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/*
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* The three following nodes are marked with opp-suspend
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* because the can not be enabled simultaneously on a
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* single SoC.
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*/
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2017-04-20 17:55:06 +07:00
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opp50-300000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <950000 931000 969000>;
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opp-supported-hw = <0x06 0x0010>;
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opp-suspend;
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};
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2017-04-20 17:55:06 +07:00
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opp100-275000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <275000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x01 0x00FF>;
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opp-suspend;
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};
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2017-04-20 17:55:06 +07:00
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opp100-300000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x06 0x0020>;
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opp-suspend;
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};
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2017-04-20 17:55:06 +07:00
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opp100-500000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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2017-04-20 17:55:06 +07:00
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opp100-600000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0x06 0x0040>;
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};
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2017-04-20 17:55:06 +07:00
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opp120-600000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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2017-04-20 17:55:06 +07:00
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opp120-720000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0x06 0x0080>;
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};
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2017-04-20 17:55:06 +07:00
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oppturbo-720000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0x01 0xFFFF>;
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};
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2017-04-20 17:55:06 +07:00
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oppturbo-800000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0x06 0x0100>;
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};
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2017-04-20 17:55:06 +07:00
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oppnitro-1000000000 {
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2017-03-06 22:23:38 +07:00
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1325000 1298500 1351500>;
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opp-supported-hw = <0x04 0x0200>;
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};
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};
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2017-08-30 22:19:52 +07:00
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pmu@4b000000 {
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2013-08-04 01:00:54 +07:00
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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2017-08-30 22:19:52 +07:00
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reg = <0x4b000000 0x1000000>;
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ti,hwmods = "debugss";
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2013-08-04 01:00:54 +07:00
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};
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2012-06-22 16:40:48 +07:00
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/*
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2014-03-28 17:11:37 +07:00
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* The soc node represents the soc top level view. It is used for IPs
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2012-06-22 16:40:48 +07:00
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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2018-02-19 10:35:01 +07:00
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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2012-06-22 16:40:48 +07:00
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};
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};
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/*
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* XXX: Use a flat representation of the AM33XX interconnect.
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2014-03-28 17:11:39 +07:00
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* The real AM33XX interconnect network is quite complex. Since
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* it will not bring real advantage to represent that in DT
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2012-06-22 16:40:48 +07:00
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* for the moment, just use a fake OCP bus entry to represent
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* the whole bus hierarchy.
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*/
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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2018-09-25 06:20:54 +07:00
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l4_wkup: interconnect@44c00000 {
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2015-07-14 00:34:54 +07:00
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am3352-wkup-m3";
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reg = <0x100000 0x4000>,
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2018-09-25 06:20:54 +07:00
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<0x180000 0x2000>;
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2015-07-14 00:34:54 +07:00
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reg-names = "umem", "dmem";
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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2018-09-25 06:20:54 +07:00
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};
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l4_per: interconnect@48000000 {
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};
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l4_fw: interconnect@47c00000 {
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};
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l4_fast: interconnect@4a000000 {
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};
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l4_mpuss: interconnect@4b140000 {
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2013-07-18 22:15:35 +07:00
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};
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2012-06-22 16:40:48 +07:00
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intc: interrupt-controller@48200000 {
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2014-09-09 07:54:48 +07:00
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compatible = "ti,am33xx-intc";
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2012-06-22 16:40:48 +07:00
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48200000 0x1000>;
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};
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2020-03-04 22:25:30 +07:00
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <20 21>;
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};
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2015-12-17 20:33:36 +07:00
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};
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2020-03-04 22:25:30 +07:00
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <112>;
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interrupt-names = "edma3_tcerrint";
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};
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2015-12-17 20:33:36 +07:00
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};
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2020-03-04 22:25:30 +07:00
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target-module@49900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49900000 0x4>,
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<0x49900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49900000 0x100000>;
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edma_tptc1: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <113>;
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interrupt-names = "edma3_tcerrint";
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};
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2015-12-17 20:33:36 +07:00
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};
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|
2020-03-04 22:25:30 +07:00
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target-module@49a00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49a00000 0x4>,
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<0x49a00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49a00000 0x100000>;
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edma_tptc2: dma@0 {
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compatible = "ti,edma3-tptc";
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|
|
reg = <0 0x100000>;
|
|
|
|
|
interrupts = <114>;
|
|
|
|
|
interrupt-names = "edma3_tcerrint";
|
|
|
|
|
};
|
2013-09-11 02:24:37 +07:00
|
|
|
};
|
|
|
|
|
|
2019-07-23 14:29:23 +07:00
|
|
|
target-module@47810000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x478102fc 0x4>,
|
|
|
|
|
<0x47810110 0x4>,
|
|
|
|
|
<0x47810114 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
|
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
|
|
|
SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x47810000 0x1000>;
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@0 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
|
|
|
|
ti,needs-special-reset;
|
|
|
|
|
interrupts = <29>;
|
|
|
|
|
reg = <0x0 0x1000>;
|
|
|
|
|
};
|
2013-09-11 02:24:39 +07:00
|
|
|
};
|
|
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
usb: target-module@47400000 {
|
|
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
|
|
|
reg = <0x47400000 0x4>,
|
|
|
|
|
<0x47400010 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
|
|
|
SYSC_OMAP2_SOFTRESET)>;
|
|
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
|
clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
2013-07-05 19:51:33 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2019-10-22 04:16:41 +07:00
|
|
|
ranges = <0x0 0x47400000 0x5000>;
|
2013-07-05 19:51:33 +07:00
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
usb0_phy: usb-phy@1300 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,am335x-usb-phy";
|
2019-10-22 04:16:41 +07:00
|
|
|
reg = <0x1300 0x100>;
|
2013-07-05 19:51:33 +07:00
|
|
|
reg-names = "phy";
|
2013-10-14 19:49:21 +07:00
|
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
2017-11-10 05:26:14 +07:00
|
|
|
#phy-cells = <0>;
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
usb0: usb@1400 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,musb-am33xx";
|
2019-10-22 04:16:41 +07:00
|
|
|
reg = <0x1400 0x400>,
|
|
|
|
|
<0x1000 0x200>;
|
2013-08-20 23:35:47 +07:00
|
|
|
reg-names = "mc", "control";
|
|
|
|
|
|
|
|
|
|
interrupts = <18>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
mentor,multipoint = <1>;
|
|
|
|
|
mentor,num-eps = <16>;
|
|
|
|
|
mentor,ram-bits = <12>;
|
|
|
|
|
mentor,power = <500>;
|
|
|
|
|
phys = <&usb0_phy>;
|
2013-06-20 17:13:04 +07:00
|
|
|
|
|
|
|
|
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
|
|
|
|
&cppi41dma 2 0 &cppi41dma 3 0
|
|
|
|
|
&cppi41dma 4 0 &cppi41dma 5 0
|
|
|
|
|
&cppi41dma 6 0 &cppi41dma 7 0
|
|
|
|
|
&cppi41dma 8 0 &cppi41dma 9 0
|
|
|
|
|
&cppi41dma 10 0 &cppi41dma 11 0
|
|
|
|
|
&cppi41dma 12 0 &cppi41dma 13 0
|
|
|
|
|
&cppi41dma 14 0 &cppi41dma 0 1
|
|
|
|
|
&cppi41dma 1 1 &cppi41dma 2 1
|
|
|
|
|
&cppi41dma 3 1 &cppi41dma 4 1
|
|
|
|
|
&cppi41dma 5 1 &cppi41dma 6 1
|
|
|
|
|
&cppi41dma 7 1 &cppi41dma 8 1
|
|
|
|
|
&cppi41dma 9 1 &cppi41dma 10 1
|
|
|
|
|
&cppi41dma 11 1 &cppi41dma 12 1
|
|
|
|
|
&cppi41dma 13 1 &cppi41dma 14 1>;
|
|
|
|
|
dma-names =
|
|
|
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
|
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
|
|
|
"rx14", "rx15",
|
|
|
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
|
|
|
"tx14", "tx15";
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
usb1_phy: usb-phy@1b00 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,am335x-usb-phy";
|
2019-10-22 04:16:41 +07:00
|
|
|
reg = <0x1b00 0x100>;
|
2013-07-05 19:51:33 +07:00
|
|
|
reg-names = "phy";
|
2013-10-14 19:49:21 +07:00
|
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
2017-11-10 05:26:14 +07:00
|
|
|
#phy-cells = <0>;
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
usb1: usb@1800 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,musb-am33xx";
|
2019-10-22 04:16:41 +07:00
|
|
|
reg = <0x1c00 0x400>,
|
|
|
|
|
<0x1800 0x200>;
|
2013-08-20 23:35:47 +07:00
|
|
|
reg-names = "mc", "control";
|
|
|
|
|
interrupts = <19>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
mentor,multipoint = <1>;
|
|
|
|
|
mentor,num-eps = <16>;
|
|
|
|
|
mentor,ram-bits = <12>;
|
|
|
|
|
mentor,power = <500>;
|
|
|
|
|
phys = <&usb1_phy>;
|
2013-06-20 17:13:04 +07:00
|
|
|
|
|
|
|
|
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
|
|
|
|
&cppi41dma 17 0 &cppi41dma 18 0
|
|
|
|
|
&cppi41dma 19 0 &cppi41dma 20 0
|
|
|
|
|
&cppi41dma 21 0 &cppi41dma 22 0
|
|
|
|
|
&cppi41dma 23 0 &cppi41dma 24 0
|
|
|
|
|
&cppi41dma 25 0 &cppi41dma 26 0
|
|
|
|
|
&cppi41dma 27 0 &cppi41dma 28 0
|
|
|
|
|
&cppi41dma 29 0 &cppi41dma 15 1
|
|
|
|
|
&cppi41dma 16 1 &cppi41dma 17 1
|
|
|
|
|
&cppi41dma 18 1 &cppi41dma 19 1
|
|
|
|
|
&cppi41dma 20 1 &cppi41dma 21 1
|
|
|
|
|
&cppi41dma 22 1 &cppi41dma 23 1
|
|
|
|
|
&cppi41dma 24 1 &cppi41dma 25 1
|
|
|
|
|
&cppi41dma 26 1 &cppi41dma 27 1
|
|
|
|
|
&cppi41dma 28 1 &cppi41dma 29 1>;
|
|
|
|
|
dma-names =
|
|
|
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
|
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
|
|
|
"rx14", "rx15",
|
|
|
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
|
|
|
"tx14", "tx15";
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
2013-06-20 17:13:04 +07:00
|
|
|
|
2019-10-22 04:16:41 +07:00
|
|
|
cppi41dma: dma-controller@2000 {
|
2013-06-20 17:13:04 +07:00
|
|
|
compatible = "ti,am3359-cppi41";
|
2019-10-22 04:16:41 +07:00
|
|
|
reg = <0x0000 0x1000>,
|
|
|
|
|
<0x2000 0x1000>,
|
|
|
|
|
<0x3000 0x1000>,
|
|
|
|
|
<0x4000 0x4000>;
|
2013-08-20 23:35:45 +07:00
|
|
|
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
2013-06-20 17:13:04 +07:00
|
|
|
interrupts = <17>;
|
|
|
|
|
interrupt-names = "glue";
|
|
|
|
|
#dma-cells = <2>;
|
|
|
|
|
#dma-channels = <30>;
|
|
|
|
|
#dma-requests = <256>;
|
|
|
|
|
};
|
2012-11-06 21:29:38 +07:00
|
|
|
};
|
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking changes from David Miller:
1) Allow to dump, monitor, and change the bridge multicast database
using netlink. From Cong Wang.
2) RFC 5961 TCP blind data injection attack mitigation, from Eric
Dumazet.
3) Networking user namespace support from Eric W. Biederman.
4) tuntap/virtio-net multiqueue support by Jason Wang.
5) Support for checksum offload of encapsulated packets (basically,
tunneled traffic can still be checksummed by HW). From Joseph
Gasparakis.
6) Allow BPF filter access to VLAN tags, from Eric Dumazet and
Daniel Borkmann.
7) Bridge port parameters over netlink and BPDU blocking support
from Stephen Hemminger.
8) Improve data access patterns during inet socket demux by rearranging
socket layout, from Eric Dumazet.
9) TIPC protocol updates and cleanups from Ying Xue, Paul Gortmaker, and
Jon Maloy.
10) Update TCP socket hash sizing to be more in line with current day
realities. The existing heurstics were choosen a decade ago.
From Eric Dumazet.
11) Fix races, queue bloat, and excessive wakeups in ATM and
associated drivers, from Krzysztof Mazur and David Woodhouse.
12) Support DOVE (Distributed Overlay Virtual Ethernet) extensions
in VXLAN driver, from David Stevens.
13) Add "oops_only" mode to netconsole, from Amerigo Wang.
14) Support set and query of VEB/VEPA bridge mode via PF_BRIDGE, also
allow DCB netlink to work on namespaces other than the initial
namespace. From John Fastabend.
15) Support PTP in the Tigon3 driver, from Matt Carlson.
16) tun/vhost zero copy fixes and improvements, plus turn it on
by default, from Michael S. Tsirkin.
17) Support per-association statistics in SCTP, from Michele
Baldessari.
And many, many, driver updates, cleanups, and improvements. Too
numerous to mention individually.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1722 commits)
net/mlx4_en: Add support for destination MAC in steering rules
net/mlx4_en: Use generic etherdevice.h functions.
net: ethtool: Add destination MAC address to flow steering API
bridge: add support of adding and deleting mdb entries
bridge: notify mdb changes via netlink
ndisc: Unexport ndisc_{build,send}_skb().
uapi: add missing netconf.h to export list
pkt_sched: avoid requeues if possible
solos-pci: fix double-free of TX skb in DMA mode
bnx2: Fix accidental reversions.
bna: Driver Version Updated to 3.1.2.1
bna: Firmware update
bna: Add RX State
bna: Rx Page Based Allocation
bna: TX Intr Coalescing Fix
bna: Tx and Rx Optimizations
bna: Code Cleanup and Enhancements
ath9k: check pdata variable before dereferencing it
ath5k: RX timestamp is reported at end of frame
ath9k_htc: RX timestamp is reported at end of frame
...
2012-12-13 09:07:07 +07:00
|
|
|
|
2019-10-21 23:17:52 +07:00
|
|
|
ocmcram: sram@40300000 {
|
2014-09-10 23:04:03 +07:00
|
|
|
compatible = "mmio-sram";
|
|
|
|
|
reg = <0x40300000 0x10000>; /* 64k */
|
2018-02-19 10:34:57 +07:00
|
|
|
ranges = <0x0 0x40300000 0x10000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
2019-10-21 23:17:52 +07:00
|
|
|
pm_sram_code: pm-code-sram@0 {
|
2018-02-19 10:34:57 +07:00
|
|
|
compatible = "ti,sram";
|
|
|
|
|
reg = <0x0 0x1000>;
|
|
|
|
|
protect-exec;
|
|
|
|
|
};
|
|
|
|
|
|
2019-10-21 23:17:52 +07:00
|
|
|
pm_sram_data: pm-data-sram@1000 {
|
2018-02-19 10:34:57 +07:00
|
|
|
compatible = "ti,sram";
|
|
|
|
|
reg = <0x1000 0x1000>;
|
|
|
|
|
pool;
|
|
|
|
|
};
|
2013-01-29 18:15:07 +07:00
|
|
|
};
|
|
|
|
|
|
2017-08-30 22:19:52 +07:00
|
|
|
emif: emif@4c000000 {
|
|
|
|
|
compatible = "ti,emif-am3352";
|
|
|
|
|
reg = <0x4c000000 0x1000000>;
|
|
|
|
|
ti,hwmods = "emif";
|
2018-02-26 22:04:59 +07:00
|
|
|
interrupts = <101>;
|
2018-02-19 10:34:59 +07:00
|
|
|
sram = <&pm_sram_code
|
|
|
|
|
&pm_sram_data>;
|
2018-02-19 10:35:03 +07:00
|
|
|
ti,no-idle;
|
2017-08-30 22:19:52 +07:00
|
|
|
};
|
|
|
|
|
|
2013-05-02 16:44:03 +07:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
|
compatible = "ti,am3352-gpmc";
|
|
|
|
|
ti,hwmods = "gpmc";
|
2013-10-15 14:07:50 +07:00
|
|
|
ti,no-idle-on-init;
|
2013-05-02 16:44:03 +07:00
|
|
|
reg = <0x50000000 0x2000>;
|
|
|
|
|
interrupts = <100>;
|
2016-03-11 06:56:38 +07:00
|
|
|
dmas = <&edma 52 0>;
|
2015-10-16 00:37:27 +07:00
|
|
|
dma-names = "rxtx";
|
2013-05-28 15:24:57 +07:00
|
|
|
gpmc,num-cs = <7>;
|
|
|
|
|
gpmc,num-waitpins = <2>;
|
2013-05-02 16:44:03 +07:00
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
2016-02-23 23:37:21 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2016-04-07 17:25:32 +07:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
2013-05-02 16:44:03 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-08-24 04:12:35 +07:00
|
|
|
|
2019-12-13 00:46:14 +07:00
|
|
|
sham_target: target-module@53100000 {
|
|
|
|
|
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
|
|
|
|
reg = <0x53100100 0x4>,
|
|
|
|
|
<0x53100110 0x4>,
|
|
|
|
|
<0x53100114 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
/* Domains (P, C): per_pwrdm, l3_clkdm */
|
|
|
|
|
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x53100000 0x1000>;
|
|
|
|
|
|
|
|
|
|
sham: sham@0 {
|
|
|
|
|
compatible = "ti,omap4-sham";
|
|
|
|
|
reg = <0 0x200>;
|
|
|
|
|
interrupts = <109>;
|
|
|
|
|
dmas = <&edma 36 0>;
|
|
|
|
|
dma-names = "rx";
|
|
|
|
|
};
|
2013-08-24 04:12:35 +07:00
|
|
|
};
|
2013-08-24 04:12:36 +07:00
|
|
|
|
2019-12-13 00:46:15 +07:00
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aes_target: target-module@53500000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x53500080 0x4>,
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<0x53500084 0x4>,
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<0x53500088 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x53500000 0x1000>;
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aes: aes@0 {
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compatible = "ti,omap4-aes";
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reg = <0 0xa0>;
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interrupts = <103>;
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dmas = <&edma 6 0>,
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<&edma 5 0>;
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dma-names = "tx", "rx";
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};
|
2013-08-24 04:12:36 +07:00
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};
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2019-08-14 20:14:08 +07:00
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target-module@56000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5600fe00 0x4>,
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<0x5600fe10 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_gfx 0>;
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reset-names = "rstctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x56000000 0x1000000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
|
2012-06-22 16:40:48 +07:00
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};
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};
|
2013-07-18 22:15:35 +07:00
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|
2018-09-25 06:20:54 +07:00
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|
|
#include "am33xx-l4.dtsi"
|
2017-12-08 22:17:30 +07:00
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|
|
#include "am33xx-clocks.dtsi"
|
2019-10-10 15:21:06 +07:00
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|
|
&prcm {
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|
prm_per: prm@c00 {
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|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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|
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reg = <0xc00 0x100>;
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|
|
#reset-cells = <1>;
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|
|
};
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|
|
prm_wkup: prm@d00 {
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|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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|
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reg = <0xd00 0x100>;
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|
|
#reset-cells = <1>;
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|
|
};
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|
|
prm_device: prm@f00 {
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|
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|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
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|
|
reg = <0xf00 0x100>;
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|
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|
|
#reset-cells = <1>;
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|
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|
|
};
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|
|
prm_gfx: prm@1100 {
|
|
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|
|
compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
|
|
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|
|
reg = <0x1100 0x100>;
|
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|
|
#reset-cells = <1>;
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|
|
|
};
|
|
|
|
|
};
|