2014-02-07 14:24:56 +07:00
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/*
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* Copyright 2013 Gateworks Corporation
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2014-09-09 13:07:28 +07:00
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#include <dt-bindings/gpio/gpio.h>
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2014-02-07 14:24:56 +07:00
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/ {
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/* these are used by bootloader for disabling nodes */
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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nand = &gpmi;
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ssi0 = &ssi1;
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usb0 = &usbh1;
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usb1 = &usbotg;
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};
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chosen {
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bootargs = "console=ttymxc1,115200";
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};
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2014-05-01 13:32:30 +07:00
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm4 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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};
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2014-02-07 14:24:56 +07:00
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leds {
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compatible = "gpio-leds";
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2014-09-09 13:07:30 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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2014-02-07 14:24:56 +07:00
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led0: user1 {
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label = "user1";
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
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2014-02-07 14:24:56 +07:00
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led1: user2 {
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label = "user2";
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
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2014-02-07 14:24:56 +07:00
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default-state = "off";
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};
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led2: user3 {
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label = "user3";
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
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2014-02-07 14:24:56 +07:00
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default-state = "off";
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};
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};
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memory {
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reg = <0x10000000 0x20000000>;
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};
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pps {
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compatible = "pps-gpio";
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2014-09-09 13:07:30 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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2014-02-07 14:24:56 +07:00
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status = "okay";
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_1p0v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "1P0V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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/* remove this fixed regulator once ltc3676__sw2 driver available */
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reg_1p8v: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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reg_3p3v: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_5p0v: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "5P0V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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reg_usb_otg_vbus: regulator@4 {
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compatible = "regulator-fixed";
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reg = <4>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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2014-09-09 13:07:28 +07:00
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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2014-02-07 14:24:56 +07:00
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enable-active-high;
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};
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};
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sound {
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2014-05-22 13:04:54 +07:00
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compatible = "fsl,imx6q-ventana-sgtl5000",
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2014-02-07 14:24:56 +07:00
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"fsl,imx-audio-sgtl5000";
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2014-05-22 13:04:54 +07:00
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model = "sgtl5000-audio";
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2014-02-07 14:24:56 +07:00
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ssi-controller = <&ssi1>;
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audio-codec = <&codec>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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mux-int-port = <1>;
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mux-ext-port = <4>;
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};
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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};
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2014-09-09 13:07:31 +07:00
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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2015-11-07 05:40:32 +07:00
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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};
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2015-11-20 03:02:24 +07:00
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&ecspi3 {
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fsl,spi-num-chipselects = <1>;
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cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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status = "okay";
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};
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2014-02-07 14:24:56 +07:00
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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2015-12-11 20:22:04 +07:00
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phy-mode = "rgmii-id";
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2014-09-09 13:07:28 +07:00
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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2014-02-07 14:24:56 +07:00
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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2014-04-23 14:47:51 +07:00
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&hdmi {
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ddc-i2c-bus = <&i2c3>;
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status = "okay";
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};
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2014-02-07 14:24:56 +07:00
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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eeprom1: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom2: eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom3: eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom4: eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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gpio: pca9555@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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rtc: ds1672@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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2016-04-27 08:28:29 +07:00
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clocks = <&clks IMX6QDL_CLK_CKO>;
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2014-02-07 14:24:56 +07:00
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VDDA-supply = <®_1p8v>;
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VDDIO-supply = <®_3p3v>;
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};
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touchscreen: egalax_ts@04 {
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compatible = "eeti,egalax_ts";
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reg = <0x04>;
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interrupt-parent = <&gpio7>;
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2014-09-09 13:07:28 +07:00
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interrupts = <12 2>;
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wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
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2014-02-07 14:24:56 +07:00
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};
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};
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2014-09-09 13:07:30 +07:00
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&ldb {
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status = "okay";
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2014-02-07 14:24:56 +07:00
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2014-09-09 13:07:30 +07:00
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lvds-channel@0 {
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fsl,data-mapping = "spwg";
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fsl,data-width = <18>;
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status = "okay";
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display-timings {
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native-mode = <&timing0>;
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timing0: hsd100pxn1 {
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clock-frequency = <65000000>;
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hactive = <1024>;
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vactive = <768>;
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hback-porch = <220>;
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hfront-porch = <40>;
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vback-porch = <21>;
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vfront-porch = <7>;
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hsync-len = <60>;
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vsync-len = <10>;
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};
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2014-02-07 14:24:56 +07:00
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};
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2014-09-09 13:07:30 +07:00
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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2015-11-20 03:02:03 +07:00
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
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status = "disabled";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
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status = "disabled";
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};
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2014-09-09 13:07:30 +07:00
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>;
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status = "okay";
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};
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&ssi1 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2014-09-09 13:07:30 +07:00
|
|
|
&uart5 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_uart5>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbotg {
|
|
|
|
|
vbus-supply = <®_usb_otg_vbus>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
|
|
|
disable-over-current;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbh1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usdhc3 {
|
2015-06-29 19:08:56 +07:00
|
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
2014-09-09 13:07:30 +07:00
|
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
2015-06-29 19:08:56 +07:00
|
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
|
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
2015-07-22 19:53:02 +07:00
|
|
|
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
2014-09-09 13:07:30 +07:00
|
|
|
vmmc-supply = <®_3p3v>;
|
2015-06-29 19:08:56 +07:00
|
|
|
no-1-8-v; /* firmware will remove if board revision supports */
|
2014-09-09 13:07:30 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&iomuxc {
|
|
|
|
|
imx6qdl-gw52xx {
|
2014-02-07 14:24:56 +07:00
|
|
|
pinctrl_audmux: audmuxgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
|
|
|
|
|
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
|
|
|
|
|
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
|
|
|
|
|
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
|
2014-09-09 13:07:30 +07:00
|
|
|
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
|
2014-02-07 14:24:56 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-11-20 03:02:24 +07:00
|
|
|
pinctrl_ecspi3: escpi3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
|
|
|
|
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
|
|
|
|
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
|
|
|
|
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-07 14:24:56 +07:00
|
|
|
pinctrl_enet: enetgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
2014-09-09 13:07:30 +07:00
|
|
|
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-09 13:07:31 +07:00
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-09 13:07:30 +07:00
|
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
2014-02-07 14:24:56 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
|
|
|
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-09 13:07:30 +07:00
|
|
|
pinctrl_pcie: pciegrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_pps: ppsgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-11-20 03:02:03 +07:00
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
|
|
|
fsl,pins = <
|
2016-01-08 00:57:46 +07:00
|
|
|
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
2015-11-20 03:02:03 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-05-01 13:32:30 +07:00
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-07 14:24:56 +07:00
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart5: uart5grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
2014-09-09 13:07:30 +07:00
|
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
|
2014-02-07 14:24:56 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
|
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
|
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
|
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
|
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
|
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
2015-06-29 19:08:56 +07:00
|
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
|
|
|
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
|
|
|
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
|
|
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
|
|
|
|
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
|
|
|
|
|
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
|
2014-02-07 14:24:56 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
