2012-08-22 20:36:29 +07:00
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* Clock bindings for Freescale i.MX28
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Required properties:
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- compatible: Should be "fsl,imx28-clkctrl"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX28
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clocks and IDs.
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Clock ID
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------------------
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ref_xtal 0
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pll0 1
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pll1 2
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pll2 3
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ref_cpu 4
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ref_emi 5
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ref_io0 6
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ref_io1 7
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ref_pix 8
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ref_hsadc 9
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ref_gpmi 10
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saif0_sel 11
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saif1_sel 12
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gpmi_sel 13
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ssp0_sel 14
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ssp1_sel 15
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ssp2_sel 16
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ssp3_sel 17
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emi_sel 18
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etm_sel 19
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lcdif_sel 20
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cpu 21
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ptp_sel 22
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cpu_pll 23
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cpu_xtal 24
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hbus 25
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xbus 26
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ssp0_div 27
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ssp1_div 28
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ssp2_div 29
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ssp3_div 30
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gpmi_div 31
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emi_pll 32
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emi_xtal 33
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lcdif_div 34
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etm_div 35
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ptp 36
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saif0_div 37
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saif1_div 38
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clk32k_div 39
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rtc 40
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lradc 41
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spdif_div 42
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clk32k 43
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pwm 44
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uart 45
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ssp0 46
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ssp1 47
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ssp2 48
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ssp3 49
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gpmi 50
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spdif 51
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emi 52
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saif0 53
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saif1 54
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lcdif 55
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etm 56
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fec 57
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can0 58
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can1 59
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usb0 60
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usb1 61
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2012-09-22 23:54:55 +07:00
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usb0_phy 62
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usb1_phy 63
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2012-08-22 20:36:29 +07:00
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enet_out 64
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Examples:
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clks: clkctrl@80040000 {
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compatible = "fsl,imx28-clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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};
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auart0: serial@8006a000 {
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compatible = "fsl,imx28-auart", "fsl,imx23-auart";
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reg = <0x8006a000 0x2000>;
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interrupts = <112 70 71>;
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clocks = <&clks 45>;
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};
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