2006-01-17 13:14:14 +07:00
|
|
|
/*
|
|
|
|
* arch/sh/kernel/cpu/irq/ipr.c
|
2005-04-17 05:20:36 +07:00
|
|
|
*
|
|
|
|
* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
|
|
|
|
* Copyright (C) 2000 Kazumoto Kojima
|
|
|
|
* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
|
|
|
|
*
|
|
|
|
* Interrupt handling for IPR-based IRQ.
|
|
|
|
*
|
|
|
|
* Supported system:
|
|
|
|
* On-chip supporting modules (TMU, RTC, etc.).
|
|
|
|
* On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
|
|
|
|
* Hitachi SolutionEngine external I/O:
|
|
|
|
* MS7709SE01, MS7709ASE01, and MS7750SE01
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/irq.h>
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
|
|
|
#include <asm/system.h>
|
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/machvec.h>
|
|
|
|
|
|
|
|
struct ipr_data {
|
|
|
|
unsigned int addr; /* Address of Interrupt Priority Register */
|
|
|
|
int shift; /* Shifts of the 16-bit data */
|
|
|
|
int priority; /* The priority */
|
|
|
|
};
|
|
|
|
static struct ipr_data ipr_data[NR_IRQS];
|
|
|
|
|
|
|
|
static void enable_ipr_irq(unsigned int irq);
|
|
|
|
static void disable_ipr_irq(unsigned int irq);
|
|
|
|
|
|
|
|
/* shutdown is same as "disable" */
|
|
|
|
#define shutdown_ipr_irq disable_ipr_irq
|
|
|
|
|
|
|
|
static void mask_and_ack_ipr(unsigned int);
|
|
|
|
static void end_ipr_irq(unsigned int irq);
|
|
|
|
|
|
|
|
static unsigned int startup_ipr_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
enable_ipr_irq(irq);
|
|
|
|
return 0; /* never anything pending */
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct hw_interrupt_type ipr_irq_type = {
|
2005-09-10 14:26:42 +07:00
|
|
|
.typename = "IPR-IRQ",
|
|
|
|
.startup = startup_ipr_irq,
|
|
|
|
.shutdown = shutdown_ipr_irq,
|
|
|
|
.enable = enable_ipr_irq,
|
|
|
|
.disable = disable_ipr_irq,
|
|
|
|
.ack = mask_and_ack_ipr,
|
|
|
|
.end = end_ipr_irq
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static void disable_ipr_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long val, flags;
|
|
|
|
unsigned int addr = ipr_data[irq].addr;
|
|
|
|
unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
|
|
|
|
|
|
|
|
/* Set the priority in IPR to 0 */
|
|
|
|
local_irq_save(flags);
|
|
|
|
val = ctrl_inw(addr);
|
|
|
|
val &= mask;
|
|
|
|
ctrl_outw(val, addr);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_ipr_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
unsigned long val, flags;
|
|
|
|
unsigned int addr = ipr_data[irq].addr;
|
|
|
|
int priority = ipr_data[irq].priority;
|
|
|
|
unsigned short value = (priority << ipr_data[irq].shift);
|
|
|
|
|
|
|
|
/* Set priority in IPR back to original value */
|
|
|
|
local_irq_save(flags);
|
|
|
|
val = ctrl_inw(addr);
|
|
|
|
val |= value;
|
|
|
|
ctrl_outw(val, addr);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mask_and_ack_ipr(unsigned int irq)
|
|
|
|
{
|
|
|
|
disable_ipr_irq(irq);
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
2006-09-27 15:38:11 +07:00
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
2005-04-17 05:20:36 +07:00
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
|
|
|
/* This is needed when we use edge triggered setting */
|
|
|
|
/* XXX: Is it really needed? */
|
|
|
|
if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
|
|
|
|
/* Clear external interrupt request */
|
|
|
|
int a = ctrl_inb(INTC_IRR0);
|
|
|
|
a &= ~(1 << (irq - IRQ0_IRQ));
|
|
|
|
ctrl_outb(a, INTC_IRR0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void end_ipr_irq(unsigned int irq)
|
|
|
|
{
|
|
|
|
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
|
|
enable_ipr_irq(irq);
|
|
|
|
}
|
|
|
|
|
2006-02-01 18:06:04 +07:00
|
|
|
void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
disable_irq_nosync(irq);
|
|
|
|
ipr_data[irq].addr = addr;
|
|
|
|
ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
|
|
|
|
ipr_data[irq].priority = priority;
|
|
|
|
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 16:24:36 +07:00
|
|
|
irq_desc[irq].chip = &ipr_irq_type;
|
2005-04-17 05:20:36 +07:00
|
|
|
disable_ipr_irq(irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init init_IRQ(void)
|
|
|
|
{
|
2006-01-17 13:14:14 +07:00
|
|
|
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
|
|
|
|
make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#if defined(CONFIG_SH_RTC)
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef SCI_ERI_IRQ
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
|
|
|
make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
|
|
|
make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef SCIF1_ERI_IRQ
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
|
|
|
|
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
|
|
|
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
|
|
|
make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef SCIF_ERI_IRQ
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
|
|
|
make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef IRDA_ERI_IRQ
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
|
|
|
make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
|
|
|
make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
|
|
|
make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
2006-09-27 15:38:11 +07:00
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
2005-04-17 05:20:36 +07:00
|
|
|
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
|
|
|
/*
|
|
|
|
* Initialize the Interrupt Controller (INTC)
|
|
|
|
* registers to their power on values
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable external irq (INTC IRQ mode).
|
|
|
|
* You should set corresponding bits of PFC to "00"
|
|
|
|
* to enable these interrupts.
|
|
|
|
*/
|
2006-02-01 18:06:04 +07:00
|
|
|
make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
|
|
|
|
make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
|
|
|
|
make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
|
|
|
|
make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
|
|
|
|
make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
|
|
|
|
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
2006-01-17 13:14:14 +07:00
|
|
|
#endif
|
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2006-01-17 13:14:14 +07:00
|
|
|
#ifdef CONFIG_CPU_HAS_PINT_IRQ
|
|
|
|
init_IRQ_pint();
|
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2006-01-17 13:14:14 +07:00
|
|
|
#ifdef CONFIG_CPU_HAS_INTC2_IRQ
|
2005-04-17 05:20:36 +07:00
|
|
|
init_IRQ_intc2();
|
|
|
|
#endif
|
|
|
|
/* Perform the machine specific initialisation */
|
2006-01-17 13:14:14 +07:00
|
|
|
if (sh_mv.mv_init_irq != NULL)
|
2005-04-17 05:20:36 +07:00
|
|
|
sh_mv.mv_init_irq();
|
|
|
|
}
|
2006-01-17 13:14:14 +07:00
|
|
|
|
|
|
|
#if !defined(CONFIG_CPU_HAS_PINT_IRQ)
|
2005-04-17 05:20:36 +07:00
|
|
|
int ipr_irq_demux(int irq)
|
|
|
|
{
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(make_ipr_irq);
|