arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: dmsc@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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2019-07-29 19:30:23 +07:00
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#power-domain-cells = <2>;
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arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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2020-03-03 23:00:29 +07:00
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mcu_conf: syscon@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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2019-06-05 23:34:33 +07:00
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x0 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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2019-07-29 19:30:23 +07:00
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
|
arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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clocks = <&k3_clks 287 0>;
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clock-names = "fclk";
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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2019-07-29 19:30:23 +07:00
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
|
arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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2019-06-14 21:50:01 +07:00
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wkup_gpio_intr: interrupt-controller2 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <14>;
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ti,sci-rm-range-girq = <0x5>;
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};
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2019-08-09 15:29:44 +07:00
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42110000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <113 0>, <113 1>, <113 2>,
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<113 3>, <113 4>, <113 5>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 113 0>;
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clock-names = "gpio";
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};
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wkup_gpio1: gpio@42100000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42100000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <114 0>, <114 1>, <114 2>,
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<114 3>, <114 4>, <114 5>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 114 0>;
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clock-names = "gpio";
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};
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2019-12-12 00:04:12 +07:00
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 194 0>;
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power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b10000 0x0 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 195 0>;
|
|
|
|
|
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wkup_i2c0: i2c@42120000 {
|
|
|
|
|
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x0 0x42120000 0x0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 197 0>;
|
|
|
|
|
power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fss: fss@47000000 {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
reg = <0x0 0x47000000 0x0 0x100>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
ospi0: spi@47040000 {
|
|
|
|
|
compatible = "ti,am654-ospi";
|
|
|
|
|
reg = <0x0 0x47040000 0x0 0x100>,
|
|
|
|
|
<0x5 0x00000000 0x1 0x0000000>;
|
|
|
|
|
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
cdns,fifo-depth = <256>;
|
|
|
|
|
cdns,fifo-width = <4>;
|
|
|
|
|
cdns,trigger-address = <0x0>;
|
|
|
|
|
clocks = <&k3_clks 103 0>;
|
|
|
|
|
assigned-clocks = <&k3_clks 103 0>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 103 2>;
|
|
|
|
|
assigned-clock-rates = <166666666>;
|
|
|
|
|
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ospi1: spi@47050000 {
|
|
|
|
|
compatible = "ti,am654-ospi";
|
|
|
|
|
reg = <0x0 0x47050000 0x0 0x100>,
|
|
|
|
|
<0x7 0x00000000 0x1 0x00000000>;
|
|
|
|
|
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
cdns,fifo-depth = <256>;
|
|
|
|
|
cdns,fifo-width = <4>;
|
|
|
|
|
cdns,trigger-address = <0x0>;
|
|
|
|
|
clocks = <&k3_clks 104 0>;
|
|
|
|
|
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tscadc0: tscadc@40200000 {
|
|
|
|
|
compatible = "ti,am3359-tscadc";
|
|
|
|
|
reg = <0x0 0x40200000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 0 1>;
|
|
|
|
|
assigned-clocks = <&k3_clks 0 3>;
|
|
|
|
|
assigned-clock-rates = <60000000>;
|
|
|
|
|
clock-names = "adc_tsc_fck";
|
2020-03-12 19:12:51 +07:00
|
|
|
dmas = <&main_udmap 0x7400>,
|
|
|
|
|
<&main_udmap 0x7401>;
|
|
|
|
|
dma-names = "fifo0", "fifo1";
|
2019-12-12 00:04:12 +07:00
|
|
|
|
|
|
|
|
adc {
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
compatible = "ti,am3359-adc";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tscadc1: tscadc@40210000 {
|
|
|
|
|
compatible = "ti,am3359-tscadc";
|
|
|
|
|
reg = <0x0 0x40210000 0x0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
clocks = <&k3_clks 1 1>;
|
|
|
|
|
assigned-clocks = <&k3_clks 1 3>;
|
|
|
|
|
assigned-clock-rates = <60000000>;
|
|
|
|
|
clock-names = "adc_tsc_fck";
|
2020-03-12 19:12:51 +07:00
|
|
|
dmas = <&main_udmap 0x7402>,
|
|
|
|
|
<&main_udmap 0x7403>;
|
|
|
|
|
dma-names = "fifo0", "fifo1";
|
2019-12-12 00:04:12 +07:00
|
|
|
|
|
|
|
|
adc {
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
compatible = "ti,am3359-adc";
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-01-23 18:45:26 +07:00
|
|
|
|
|
|
|
|
mcu_navss {
|
|
|
|
|
compatible = "simple-mfd";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
dma-ranges;
|
|
|
|
|
|
|
|
|
|
ti,sci-dev-id = <232>;
|
|
|
|
|
|
|
|
|
|
mcu_ringacc: ringacc@2b800000 {
|
|
|
|
|
compatible = "ti,am654-navss-ringacc";
|
|
|
|
|
reg = <0x0 0x2b800000 0x0 0x400000>,
|
|
|
|
|
<0x0 0x2b000000 0x0 0x400000>,
|
|
|
|
|
<0x0 0x28590000 0x0 0x100>,
|
|
|
|
|
<0x0 0x2a500000 0x0 0x40000>;
|
|
|
|
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
|
|
|
|
ti,num-rings = <286>;
|
|
|
|
|
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <235>;
|
|
|
|
|
msi-parent = <&main_udmass_inta>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcu_udmap: dma-controller@285c0000 {
|
|
|
|
|
compatible = "ti,j721e-navss-mcu-udmap";
|
|
|
|
|
reg = <0x0 0x285c0000 0x0 0x100>,
|
|
|
|
|
<0x0 0x2a800000 0x0 0x40000>,
|
|
|
|
|
<0x0 0x2aa00000 0x0 0x40000>;
|
|
|
|
|
reg-names = "gcfg", "rchanrt", "tchanrt";
|
|
|
|
|
msi-parent = <&main_udmass_inta>;
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <236>;
|
|
|
|
|
ti,ringacc = <&mcu_ringacc>;
|
|
|
|
|
|
|
|
|
|
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
|
|
|
|
<0x0f>; /* TX_HCHAN */
|
|
|
|
|
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
|
|
|
|
<0x0b>; /* RX_HCHAN */
|
|
|
|
|
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-03-24 05:52:52 +07:00
|
|
|
|
|
|
|
|
mcu_cpsw: ethernet@46000000 {
|
|
|
|
|
compatible = "ti,j721e-cpsw-nuss";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
reg = <0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
reg-names = "cpsw_nuss";
|
|
|
|
|
ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
clocks = <&k3_clks 18 22>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
|
|
|
|
|
|
|
|
|
|
dmas = <&mcu_udmap 0xf000>,
|
|
|
|
|
<&mcu_udmap 0xf001>,
|
|
|
|
|
<&mcu_udmap 0xf002>,
|
|
|
|
|
<&mcu_udmap 0xf003>,
|
|
|
|
|
<&mcu_udmap 0xf004>,
|
|
|
|
|
<&mcu_udmap 0xf005>,
|
|
|
|
|
<&mcu_udmap 0xf006>,
|
|
|
|
|
<&mcu_udmap 0xf007>,
|
|
|
|
|
<&mcu_udmap 0x7000>;
|
|
|
|
|
dma-names = "tx0", "tx1", "tx2", "tx3",
|
|
|
|
|
"tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"rx";
|
|
|
|
|
|
|
|
|
|
ethernet-ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
cpsw_port1: port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
ti,mac-only;
|
|
|
|
|
label = "port1";
|
|
|
|
|
ti,syscon-efuse = <&mcu_conf 0x200>;
|
|
|
|
|
phys = <&phy_gmii_sel 1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
davinci_mdio: mdio@f00 {
|
|
|
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
|
|
|
reg = <0x0 0xf00 0x0 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&k3_clks 18 22>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
bus_freq = <1000000>;
|
|
|
|
|
};
|
2020-05-02 03:50:10 +07:00
|
|
|
|
2020-05-07 01:14:01 +07:00
|
|
|
cpts@3d000 {
|
|
|
|
|
compatible = "ti,am65-cpts";
|
|
|
|
|
reg = <0x0 0x3d000 0x0 0x400>;
|
2020-05-02 03:50:10 +07:00
|
|
|
clocks = <&k3_clks 18 2>;
|
|
|
|
|
clock-names = "cpts";
|
|
|
|
|
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cpts";
|
|
|
|
|
ti,cpts-ext-ts-inputs = <4>;
|
|
|
|
|
ti,cpts-periodic-outputs = <2>;
|
|
|
|
|
};
|
2020-03-24 05:52:52 +07:00
|
|
|
};
|
arm64: dts: ti: Add Support for J721E SoC
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-05-22 23:19:18 +07:00
|
|
|
};
|