2007-08-08 21:57:08 +07:00
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/*
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* AVR32 SMC/CFC PATA Driver
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*
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* Copyright (C) 2007 Atmel Norway
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*/
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2007-08-08 21:57:08 +07:00
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#include <scsi/scsi_host.h>
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#include <linux/ata.h>
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#include <linux/libata.h>
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#include <linux/err.h>
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#include <linux/io.h>
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2008-08-05 18:57:38 +07:00
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#include <mach/board.h>
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#include <mach/smc.h>
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2007-08-08 21:57:08 +07:00
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#define DRV_NAME "pata_at32"
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2007-11-29 18:01:51 +07:00
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#define DRV_VERSION "0.0.3"
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2007-08-08 21:57:08 +07:00
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/*
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* CompactFlash controller memory layout relative to the base address:
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*
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* Attribute memory: 0000 0000 -> 003f ffff
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* Common memory: 0040 0000 -> 007f ffff
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* I/O memory: 0080 0000 -> 00bf ffff
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* True IDE Mode: 00c0 0000 -> 00df ffff
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* Alt IDE Mode: 00e0 0000 -> 00ff ffff
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*
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* Only True IDE and Alt True IDE mode are needed for this driver.
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*
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* True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
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* Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
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*/
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#define CF_IDE_OFFSET 0x00c00000
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#define CF_ALT_IDE_OFFSET 0x00e00000
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#define CF_RES_SIZE 2048
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/*
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* Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
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* adaptor with a logic analyzer or similar.
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*/
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#undef DEBUG_BUS
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/*
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* ATA PIO modes
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*
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* Name | Mb/s | Min cycle time | Mask
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* --------+-------+----------------+--------
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* Mode 0 | 3.3 | 600 ns | 0x01
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* Mode 1 | 5.2 | 383 ns | 0x03
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* Mode 2 | 8.3 | 240 ns | 0x07
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* Mode 3 | 11.1 | 180 ns | 0x0f
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* Mode 4 | 16.7 | 120 ns | 0x1f
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2007-11-29 18:01:51 +07:00
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*
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* Alter PIO_MASK below according to table to set maximal PIO mode.
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2007-08-08 21:57:08 +07:00
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*/
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2009-03-15 03:38:24 +07:00
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enum {
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PIO_MASK = ATA_PIO4,
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};
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2007-08-08 21:57:08 +07:00
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/*
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* Struct containing private information about device.
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*/
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struct at32_ide_info {
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unsigned int irq;
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struct resource res_ide;
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struct resource res_alt;
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void __iomem *ide_addr;
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void __iomem *alt_addr;
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unsigned int cs;
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struct smc_config smc;
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};
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/*
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* Setup SMC for the given ATA timing.
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*/
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static int pata_at32_setup_timing(struct device *dev,
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struct at32_ide_info *info,
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2007-11-29 18:01:51 +07:00
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const struct ata_timing *ata)
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2007-08-08 21:57:08 +07:00
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{
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struct smc_config *smc = &info->smc;
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2007-11-29 18:01:51 +07:00
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struct smc_timing timing;
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2007-08-08 21:57:08 +07:00
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int active;
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int recover;
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2007-11-29 18:01:51 +07:00
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memset(&timing, 0, sizeof(struct smc_timing));
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2007-08-08 21:57:08 +07:00
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/* Total cycle time */
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2007-11-29 18:01:51 +07:00
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timing.read_cycle = ata->cyc8b;
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2007-08-08 21:57:08 +07:00
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/* DIOR <= CFIOR timings */
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2007-11-29 18:01:51 +07:00
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timing.nrd_setup = ata->setup;
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timing.nrd_pulse = ata->act8b;
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timing.nrd_recover = ata->rec8b;
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/* Convert nanosecond timing to clock cycles */
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smc_set_timing(smc, &timing);
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2007-08-08 21:57:08 +07:00
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2007-11-29 18:01:51 +07:00
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/* Add one extra cycle setup due to signal ring */
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smc->nrd_setup = smc->nrd_setup + 1;
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active = smc->nrd_setup + smc->nrd_pulse;
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2007-08-08 21:57:08 +07:00
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recover = smc->read_cycle - active;
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2007-11-29 18:01:51 +07:00
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/* Need at least two cycles recovery */
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if (recover < 2)
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smc->read_cycle = active + 2;
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2007-08-08 21:57:08 +07:00
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/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
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2007-11-29 18:01:51 +07:00
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smc->ncs_read_setup = 1;
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smc->ncs_read_pulse = smc->read_cycle - 2;
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2007-08-08 21:57:08 +07:00
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/* Write timings same as read timings */
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smc->write_cycle = smc->read_cycle;
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smc->nwe_setup = smc->nrd_setup;
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smc->nwe_pulse = smc->nrd_pulse;
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smc->ncs_write_setup = smc->ncs_read_setup;
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smc->ncs_write_pulse = smc->ncs_read_pulse;
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2007-11-29 18:01:51 +07:00
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/* Do some debugging output of ATA and SMC timings */
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dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
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ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
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dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
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2007-08-08 21:57:08 +07:00
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smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
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2007-11-29 18:01:51 +07:00
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smc->ncs_read_setup, smc->ncs_read_pulse);
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2007-08-08 21:57:08 +07:00
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/* Finally, configure the SMC */
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return smc_set_configuration(info->cs, smc);
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}
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/*
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* Procedures for libATA.
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*/
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static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct ata_timing timing;
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struct at32_ide_info *info = ap->host->private_data;
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int ret;
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/* Compute ATA timing */
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ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
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if (ret) {
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dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
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return;
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}
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/* Setup SMC to ATA timing */
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ret = pata_at32_setup_timing(ap->dev, info, &timing);
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if (ret) {
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dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
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return;
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}
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}
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static struct scsi_host_template at32_sht = {
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2008-03-25 10:22:49 +07:00
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ATA_PIO_SHT(DRV_NAME),
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2007-08-08 21:57:08 +07:00
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};
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static struct ata_port_operations at32_port_ops = {
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libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
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.inherits = &ata_sff_port_ops,
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2007-08-08 21:57:08 +07:00
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.cable_detect = ata_cable_40wire,
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libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
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.set_piomode = pata_at32_set_piomode,
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2007-08-08 21:57:08 +07:00
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};
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static int __init pata_at32_init_one(struct device *dev,
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struct at32_ide_info *info)
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{
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struct ata_host *host;
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struct ata_port *ap;
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host = ata_host_alloc(dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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/* Setup ATA bindings */
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ap->ops = &at32_port_ops;
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ap->pio_mask = PIO_MASK;
|
2007-11-29 18:01:51 +07:00
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ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS;
|
2007-08-08 21:57:08 +07:00
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/*
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* Since all 8-bit taskfile transfers has to go on the lower
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* byte of the data bus and there is a bug in the SMC that
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* makes it impossible to alter the bus width during runtime,
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* we need to hardwire the address signals as follows:
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*
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* A_IDE(2:0) <= A_EBI(3:1)
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*
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* This makes all addresses on the EBI even, thus all data
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* will be on the lower byte of the data bus. All addresses
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* used by libATA need to be altered according to this.
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*/
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ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
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ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
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ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
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ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
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ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
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ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
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ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
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ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
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ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
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ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
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ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
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ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
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/* Set info as private data of ATA host */
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host->private_data = info;
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/* Register ATA device and return */
|
2008-04-07 20:47:16 +07:00
|
|
|
return ata_host_activate(host, info->irq, ata_sff_interrupt,
|
2007-08-08 21:57:08 +07:00
|
|
|
IRQF_SHARED | IRQF_TRIGGER_RISING,
|
|
|
|
&at32_sht);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function may come in handy for people analyzing their own
|
|
|
|
* EBI -> PATA adaptors.
|
|
|
|
*/
|
|
|
|
#ifdef DEBUG_BUS
|
|
|
|
|
|
|
|
static void __init pata_at32_debug_bus(struct device *dev,
|
|
|
|
struct at32_ide_info *info)
|
|
|
|
{
|
|
|
|
const int d1 = 0xff;
|
|
|
|
const int d2 = 0x00;
|
|
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Write 8-bit values (registers) */
|
|
|
|
iowrite8(d1, info->alt_addr + (0x06 << 1));
|
|
|
|
iowrite8(d2, info->alt_addr + (0x06 << 1));
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
iowrite8(d1, info->ide_addr + (i << 1));
|
|
|
|
iowrite8(d2, info->ide_addr + (i << 1));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write 16 bit values (data) */
|
|
|
|
iowrite16(d1, info->ide_addr);
|
|
|
|
iowrite16(d1 << 8, info->ide_addr);
|
|
|
|
|
|
|
|
iowrite16(d1, info->ide_addr);
|
|
|
|
iowrite16(d1 << 8, info->ide_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int __init pata_at32_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
const struct ata_timing initial_timing =
|
|
|
|
{XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
|
|
|
|
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct at32_ide_info *info;
|
|
|
|
struct ide_platform_data *board = pdev->dev.platform_data;
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
int irq;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!board)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
/* Retrive IRQ */
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0)
|
|
|
|
return irq;
|
|
|
|
|
2008-02-03 22:08:11 +07:00
|
|
|
/* Setup struct containing private information */
|
2007-08-08 21:57:08 +07:00
|
|
|
info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
|
|
|
|
if (!info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
info->irq = irq;
|
|
|
|
info->cs = board->cs;
|
|
|
|
|
|
|
|
/* Request memory resources */
|
|
|
|
info->res_ide.start = res->start + CF_IDE_OFFSET;
|
|
|
|
info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
|
|
|
|
info->res_ide.name = "ide";
|
|
|
|
info->res_ide.flags = IORESOURCE_MEM;
|
|
|
|
|
|
|
|
ret = request_resource(res, &info->res_ide);
|
|
|
|
if (ret)
|
|
|
|
goto err_req_res_ide;
|
|
|
|
|
|
|
|
info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
|
|
|
|
info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
|
|
|
|
info->res_alt.name = "alt";
|
|
|
|
info->res_alt.flags = IORESOURCE_MEM;
|
|
|
|
|
|
|
|
ret = request_resource(res, &info->res_alt);
|
|
|
|
if (ret)
|
|
|
|
goto err_req_res_alt;
|
|
|
|
|
|
|
|
/* Setup non-timing elements of SMC */
|
|
|
|
info->smc.bus_width = 2; /* 16 bit data bus */
|
|
|
|
info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
|
|
|
|
info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
|
|
|
|
info->smc.nwait_mode = 3; /* NWAIT is in READY mode */
|
|
|
|
info->smc.byte_write = 0; /* Byte select access type */
|
|
|
|
info->smc.tdf_mode = 0; /* TDF optimization disabled */
|
|
|
|
info->smc.tdf_cycles = 0; /* No TDF wait cycles */
|
|
|
|
|
2007-11-29 18:01:51 +07:00
|
|
|
/* Setup SMC to ATA timing */
|
2007-08-08 21:57:08 +07:00
|
|
|
ret = pata_at32_setup_timing(dev, info, &initial_timing);
|
|
|
|
if (ret)
|
|
|
|
goto err_setup_timing;
|
|
|
|
|
2007-11-29 18:01:51 +07:00
|
|
|
/* Map ATA address space */
|
2007-08-08 21:57:08 +07:00
|
|
|
ret = -ENOMEM;
|
|
|
|
info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
|
|
|
|
info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
|
|
|
|
if (!info->ide_addr || !info->alt_addr)
|
|
|
|
goto err_ioremap;
|
|
|
|
|
|
|
|
#ifdef DEBUG_BUS
|
|
|
|
pata_at32_debug_bus(dev, info);
|
|
|
|
#endif
|
|
|
|
|
2007-11-29 18:01:51 +07:00
|
|
|
/* Setup and register ATA device */
|
2007-08-08 21:57:08 +07:00
|
|
|
ret = pata_at32_init_one(dev, info);
|
|
|
|
if (ret)
|
|
|
|
goto err_ata_device;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_ata_device:
|
|
|
|
err_ioremap:
|
|
|
|
err_setup_timing:
|
|
|
|
release_resource(&info->res_alt);
|
|
|
|
err_req_res_alt:
|
|
|
|
release_resource(&info->res_ide);
|
|
|
|
err_req_res_ide:
|
|
|
|
kfree(info);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __exit pata_at32_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = platform_get_drvdata(pdev);
|
|
|
|
struct at32_ide_info *info;
|
|
|
|
|
|
|
|
if (!host)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
info = host->private_data;
|
|
|
|
ata_host_detach(host);
|
|
|
|
|
|
|
|
if (!info)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
release_resource(&info->res_ide);
|
|
|
|
release_resource(&info->res_alt);
|
|
|
|
|
|
|
|
kfree(info);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-04-19 03:41:57 +07:00
|
|
|
/* work with hotplug and coldplug */
|
|
|
|
MODULE_ALIAS("platform:at32_ide");
|
|
|
|
|
2007-08-08 21:57:08 +07:00
|
|
|
static struct platform_driver pata_at32_driver = {
|
|
|
|
.remove = __exit_p(pata_at32_remove),
|
|
|
|
.driver = {
|
|
|
|
.name = "at32_ide",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init pata_at32_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit pata_at32_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&pata_at32_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(pata_at32_init);
|
|
|
|
module_exit(pata_at32_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
|
|
|
|
MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|