2013-03-26 08:34:24 +07:00
|
|
|
/*
|
|
|
|
|
* r8a73a4 processor support
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2013 Renesas Solutions Corp.
|
|
|
|
|
* Copyright (C) 2013 Magnus Damm
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation; version 2 of the License.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
|
|
|
*/
|
|
|
|
|
#include <linux/irq.h>
|
|
|
|
|
#include <linux/irqchip.h>
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
|
#include <linux/of_platform.h>
|
2013-03-26 08:34:33 +07:00
|
|
|
#include <linux/serial_sci.h>
|
2013-03-26 08:34:24 +07:00
|
|
|
#include <mach/common.h>
|
|
|
|
|
#include <mach/irqs.h>
|
|
|
|
|
#include <mach/r8a73a4.h>
|
|
|
|
|
#include <asm/mach/arch.h>
|
|
|
|
|
|
2013-03-26 08:34:33 +07:00
|
|
|
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
|
|
|
|
.type = scif_type, \
|
|
|
|
|
.mapbase = baseaddr, \
|
|
|
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
|
|
|
|
.scbrr_algo_id = SCBRR_ALGO_4, \
|
|
|
|
|
.irqs = SCIx_IRQ_MUXED(irq)
|
|
|
|
|
|
|
|
|
|
#define SCIFA_DATA(index, baseaddr, irq) \
|
|
|
|
|
[index] = { \
|
|
|
|
|
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
|
|
|
|
|
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define SCIFB_DATA(index, baseaddr, irq) \
|
|
|
|
|
[index] = { \
|
|
|
|
|
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
|
|
|
|
|
.scscr = SCSCR_RE | SCSCR_TE, \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
|
|
|
|
|
|
|
|
|
|
static const struct plat_sci_port scif[] = {
|
|
|
|
|
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
|
|
|
|
|
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
|
|
|
|
|
SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
|
|
|
|
|
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
|
|
|
|
|
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
|
|
|
|
|
SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static inline void r8a73a4_register_scif(int idx)
|
|
|
|
|
{
|
|
|
|
|
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
|
|
|
|
|
sizeof(struct plat_sci_port));
|
|
|
|
|
}
|
|
|
|
|
|
2013-03-26 08:34:24 +07:00
|
|
|
void __init r8a73a4_add_standard_devices(void)
|
|
|
|
|
{
|
2013-03-26 08:34:33 +07:00
|
|
|
r8a73a4_register_scif(SCIFA0);
|
|
|
|
|
r8a73a4_register_scif(SCIFA1);
|
|
|
|
|
r8a73a4_register_scif(SCIFB0);
|
|
|
|
|
r8a73a4_register_scif(SCIFB1);
|
|
|
|
|
r8a73a4_register_scif(SCIFB2);
|
|
|
|
|
r8a73a4_register_scif(SCIFB3);
|
2013-03-26 08:34:24 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
|
|
|
void __init r8a73a4_add_standard_devices_dt(void)
|
|
|
|
|
{
|
|
|
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const char *r8a73a4_boards_compat_dt[] __initdata = {
|
|
|
|
|
"renesas,r8a73a4",
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
|
|
|
|
|
.init_irq = irqchip_init,
|
|
|
|
|
.init_machine = r8a73a4_add_standard_devices_dt,
|
|
|
|
|
.init_time = shmobile_timer_init,
|
|
|
|
|
.dt_compat = r8a73a4_boards_compat_dt,
|
|
|
|
|
MACHINE_END
|
|
|
|
|
#endif /* CONFIG_USE_OF */
|
