2005-04-17 05:20:36 +07:00
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/*
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* arch/ppc/kernel/traps.c
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras (paulus@cs.anu.edu.au)
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*/
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/*
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* This file handles the architecture-dependent parts of hardware exceptions
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/a.out.h>
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#include <linux/interrupt.h>
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/prctl.h>
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#include <asm/pgtable.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/reg.h>
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#include <asm/xmon.h>
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#ifdef CONFIG_PMAC_BACKLIGHT
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#include <asm/backlight.h>
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#endif
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#include <asm/perfmon.h>
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#ifdef CONFIG_XMON
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void (*debugger)(struct pt_regs *regs) = xmon;
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int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
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int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
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int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
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int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
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void (*debugger_fault_handler)(struct pt_regs *regs);
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#else
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#ifdef CONFIG_KGDB
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void (*debugger)(struct pt_regs *regs);
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int (*debugger_bpt)(struct pt_regs *regs);
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int (*debugger_sstep)(struct pt_regs *regs);
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int (*debugger_iabr_match)(struct pt_regs *regs);
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int (*debugger_dabr_match)(struct pt_regs *regs);
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void (*debugger_fault_handler)(struct pt_regs *regs);
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#else
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#define debugger(regs) do { } while (0)
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#define debugger_bpt(regs) 0
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#define debugger_sstep(regs) 0
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#define debugger_iabr_match(regs) 0
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#define debugger_dabr_match(regs) 0
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#define debugger_fault_handler ((void (*)(struct pt_regs *))0)
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#endif
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#endif
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/*
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* Trap & Exception support
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*/
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DEFINE_SPINLOCK(die_lock);
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void die(const char * str, struct pt_regs * fp, long err)
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{
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static int die_counter;
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int nl = 0;
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console_verbose();
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spin_lock_irq(&die_lock);
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#ifdef CONFIG_PMAC_BACKLIGHT
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set_backlight_enable(1);
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set_backlight_level(BACKLIGHT_MAX);
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#endif
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printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
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#ifdef CONFIG_PREEMPT
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printk("PREEMPT ");
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nl = 1;
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#endif
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#ifdef CONFIG_SMP
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printk("SMP NR_CPUS=%d ", NR_CPUS);
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nl = 1;
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#endif
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if (nl)
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printk("\n");
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show_regs(fp);
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spin_unlock_irq(&die_lock);
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/* do_exit() should take care of panic'ing from an interrupt
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* context so we don't handle it here
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*/
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do_exit(err);
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}
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void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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{
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siginfo_t info;
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if (!user_mode(regs)) {
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debugger(regs);
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die("Exception in kernel mode", regs, signr);
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}
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info.si_signo = signr;
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info.si_errno = 0;
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info.si_code = code;
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info.si_addr = (void __user *) addr;
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force_sig_info(signr, &info, current);
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}
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/*
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* I/O accesses can cause machine checks on powermacs.
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* Check if the NIP corresponds to the address of a sync
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* instruction for which there is an entry in the exception
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* table.
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* Note that the 601 only takes a machine check on TEA
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* (transfer error ack) signal assertion, and does not
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* set any of the top 16 bits of SRR1.
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* -- paulus.
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*/
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static inline int check_io_access(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_PMAC
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unsigned long msr = regs->msr;
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const struct exception_table_entry *entry;
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unsigned int *nip = (unsigned int *)regs->nip;
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if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
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&& (entry = search_exception_tables(regs->nip)) != NULL) {
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/*
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* Check that it's a sync instruction, or somewhere
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* in the twi; isync; nop sequence that inb/inw/inl uses.
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* As the address is in the exception table
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* we should be able to read the instr there.
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* For the debug message, we look at the preceding
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* load or store.
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*/
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if (*nip == 0x60000000) /* nop */
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nip -= 2;
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else if (*nip == 0x4c00012c) /* isync */
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--nip;
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if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
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/* sync or twi */
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unsigned int rb;
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--nip;
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rb = (*nip >> 11) & 0x1f;
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printk(KERN_DEBUG "%s bad port %lx at %p\n",
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(*nip & 0x100)? "OUT to": "IN from",
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regs->gpr[rb] - _IO_BASE, nip);
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regs->msr |= MSR_RI;
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regs->nip = entry->fixup;
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return 1;
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}
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}
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#endif /* CONFIG_PPC_PMAC */
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return 0;
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}
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#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
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/* On 4xx, the reason for the machine check or program exception
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is in the ESR. */
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#define get_reason(regs) ((regs)->dsisr)
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#ifndef CONFIG_E500
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#define get_mc_reason(regs) ((regs)->dsisr)
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#else
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#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
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#endif
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#define REASON_FP 0
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#define REASON_ILLEGAL ESR_PIL
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#define REASON_PRIVILEGED ESR_PPR
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#define REASON_TRAP ESR_PTR
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/* single-step stuff */
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#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
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#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
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#else
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/* On non-4xx, the reason for the machine check or program
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exception is in the MSR. */
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#define get_reason(regs) ((regs)->msr)
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#define get_mc_reason(regs) ((regs)->msr)
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#define REASON_FP 0x100000
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#define REASON_ILLEGAL 0x80000
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#define REASON_PRIVILEGED 0x40000
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#define REASON_TRAP 0x20000
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#define single_stepping(regs) ((regs)->msr & MSR_SE)
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#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
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#endif
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/*
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* This is "fall-back" implementation for configurations
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* which don't provide platform-specific machine check info
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*/
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void __attribute__ ((weak))
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platform_machine_check(struct pt_regs *regs)
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{
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}
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void MachineCheckException(struct pt_regs *regs)
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{
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unsigned long reason = get_mc_reason(regs);
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if (user_mode(regs)) {
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regs->msr |= MSR_RI;
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_exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
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return;
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}
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#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
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/* the qspan pci read routines can cause machine checks -- Cort */
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bad_page_fault(regs, regs->dar, SIGBUS);
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return;
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#endif
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if (debugger_fault_handler) {
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debugger_fault_handler(regs);
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regs->msr |= MSR_RI;
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return;
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}
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if (check_io_access(regs))
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return;
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#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
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if (reason & ESR_IMCP) {
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printk("Instruction");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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} else
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printk("Data");
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printk(" machine check in kernel mode.\n");
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#elif defined(CONFIG_440A)
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printk("Machine check in kernel mode.\n");
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if (reason & ESR_IMCP){
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printk("Instruction Synchronous Machine Check exception\n");
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mtspr(SPRN_ESR, reason & ~ESR_IMCP);
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}
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else {
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u32 mcsr = mfspr(SPRN_MCSR);
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if (mcsr & MCSR_IB)
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printk("Instruction Read PLB Error\n");
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if (mcsr & MCSR_DRB)
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printk("Data Read PLB Error\n");
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if (mcsr & MCSR_DWB)
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printk("Data Write PLB Error\n");
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if (mcsr & MCSR_TLBP)
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printk("TLB Parity Error\n");
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if (mcsr & MCSR_ICP){
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flush_instruction_cache();
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printk("I-Cache Parity Error\n");
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}
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if (mcsr & MCSR_DCSP)
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printk("D-Cache Search Parity Error\n");
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if (mcsr & MCSR_DCFP)
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printk("D-Cache Flush Parity Error\n");
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if (mcsr & MCSR_IMPE)
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printk("Machine Check exception is imprecise\n");
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/* Clear MCSR */
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mtspr(SPRN_MCSR, mcsr);
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}
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#elif defined (CONFIG_E500)
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printk("Machine check in kernel mode.\n");
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printk("Caused by (from MCSR=%lx): ", reason);
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if (reason & MCSR_MCP)
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printk("Machine Check Signal\n");
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if (reason & MCSR_ICPERR)
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printk("Instruction Cache Parity Error\n");
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if (reason & MCSR_DCP_PERR)
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printk("Data Cache Push Parity Error\n");
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if (reason & MCSR_DCPERR)
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printk("Data Cache Parity Error\n");
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if (reason & MCSR_GL_CI)
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printk("Guarded Load or Cache-Inhibited stwcx.\n");
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if (reason & MCSR_BUS_IAERR)
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printk("Bus - Instruction Address Error\n");
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if (reason & MCSR_BUS_RAERR)
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printk("Bus - Read Address Error\n");
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if (reason & MCSR_BUS_WAERR)
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printk("Bus - Write Address Error\n");
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if (reason & MCSR_BUS_IBERR)
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printk("Bus - Instruction Data Error\n");
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if (reason & MCSR_BUS_RBERR)
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printk("Bus - Read Data Bus Error\n");
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if (reason & MCSR_BUS_WBERR)
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printk("Bus - Read Data Bus Error\n");
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if (reason & MCSR_BUS_IPERR)
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printk("Bus - Instruction Parity Error\n");
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if (reason & MCSR_BUS_RPERR)
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printk("Bus - Read Parity Error\n");
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#else /* !CONFIG_4xx && !CONFIG_E500 */
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printk("Machine check in kernel mode.\n");
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printk("Caused by (from SRR1=%lx): ", reason);
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switch (reason & 0x601F0000) {
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case 0x80000:
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printk("Machine check signal\n");
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break;
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case 0: /* for 601 */
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case 0x40000:
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case 0x140000: /* 7450 MSS error and TEA */
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printk("Transfer error ack signal\n");
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break;
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case 0x20000:
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printk("Data parity error signal\n");
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break;
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case 0x10000:
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printk("Address parity error signal\n");
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break;
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case 0x20000000:
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printk("L1 Data Cache error\n");
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break;
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case 0x40000000:
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printk("L1 Instruction Cache error\n");
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break;
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case 0x00100000:
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printk("L2 data cache parity error\n");
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break;
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default:
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printk("Unknown values in msr\n");
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}
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#endif /* CONFIG_4xx */
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/*
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* Optional platform-provided routine to print out
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* additional info, e.g. bus error registers.
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*/
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platform_machine_check(regs);
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debugger(regs);
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die("machine check", regs, SIGBUS);
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}
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void SMIException(struct pt_regs *regs)
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{
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debugger(regs);
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#if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
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show_regs(regs);
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panic("System Management Interrupt");
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#endif
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}
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void UnknownException(struct pt_regs *regs)
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{
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printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
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regs->nip, regs->msr, regs->trap, print_tainted());
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_exception(SIGTRAP, regs, 0, 0);
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}
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void InstructionBreakpoint(struct pt_regs *regs)
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{
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|
if (debugger_iabr_match(regs))
|
|
|
|
return;
|
|
|
|
_exception(SIGTRAP, regs, TRAP_BRKPT, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void RunModeException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
_exception(SIGTRAP, regs, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Illegal instruction emulation support. Originally written to
|
|
|
|
* provide the PVR to user applications using the mfspr rd, PVR.
|
|
|
|
* Return non-zero if we can't emulate, or -EFAULT if the associated
|
|
|
|
* memory access caused an access fault. Return zero on success.
|
|
|
|
*
|
|
|
|
* There are a couple of ways to do this, either "decode" the instruction
|
|
|
|
* or directly match lots of bits. In this case, matching lots of
|
|
|
|
* bits is faster and easier.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
#define INST_MFSPR_PVR 0x7c1f42a6
|
|
|
|
#define INST_MFSPR_PVR_MASK 0xfc1fffff
|
|
|
|
|
|
|
|
#define INST_DCBA 0x7c0005ec
|
|
|
|
#define INST_DCBA_MASK 0x7c0007fe
|
|
|
|
|
|
|
|
#define INST_MCRXR 0x7c000400
|
|
|
|
#define INST_MCRXR_MASK 0x7c0007fe
|
|
|
|
|
|
|
|
#define INST_STRING 0x7c00042a
|
|
|
|
#define INST_STRING_MASK 0x7c0007fe
|
|
|
|
#define INST_STRING_GEN_MASK 0x7c00067e
|
|
|
|
#define INST_LSWI 0x7c0004aa
|
|
|
|
#define INST_LSWX 0x7c00042a
|
|
|
|
#define INST_STSWI 0x7c0005aa
|
|
|
|
#define INST_STSWX 0x7c00052a
|
|
|
|
|
|
|
|
static int emulate_string_inst(struct pt_regs *regs, u32 instword)
|
|
|
|
{
|
|
|
|
u8 rT = (instword >> 21) & 0x1f;
|
|
|
|
u8 rA = (instword >> 16) & 0x1f;
|
|
|
|
u8 NB_RB = (instword >> 11) & 0x1f;
|
|
|
|
u32 num_bytes;
|
|
|
|
u32 EA;
|
|
|
|
int pos = 0;
|
|
|
|
|
|
|
|
/* Early out if we are an invalid form of lswx */
|
|
|
|
if ((instword & INST_STRING_MASK) == INST_LSWX)
|
|
|
|
if ((rA >= rT) || (NB_RB >= rT) || (rT == rA) || (rT == NB_RB))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Early out if we are an invalid form of lswi */
|
|
|
|
if ((instword & INST_STRING_MASK) == INST_LSWI)
|
|
|
|
if ((rA >= rT) || (rT == rA))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
EA = (rA == 0) ? 0 : regs->gpr[rA];
|
|
|
|
|
|
|
|
switch (instword & INST_STRING_MASK) {
|
|
|
|
case INST_LSWX:
|
|
|
|
case INST_STSWX:
|
|
|
|
EA += NB_RB;
|
|
|
|
num_bytes = regs->xer & 0x7f;
|
|
|
|
break;
|
|
|
|
case INST_LSWI:
|
|
|
|
case INST_STSWI:
|
|
|
|
num_bytes = (NB_RB == 0) ? 32 : NB_RB;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (num_bytes != 0)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
u32 shift = 8 * (3 - (pos & 0x3));
|
|
|
|
|
|
|
|
switch ((instword & INST_STRING_MASK)) {
|
|
|
|
case INST_LSWX:
|
|
|
|
case INST_LSWI:
|
|
|
|
if (get_user(val, (u8 __user *)EA))
|
|
|
|
return -EFAULT;
|
|
|
|
/* first time updating this reg,
|
|
|
|
* zero it out */
|
|
|
|
if (pos == 0)
|
|
|
|
regs->gpr[rT] = 0;
|
|
|
|
regs->gpr[rT] |= val << shift;
|
|
|
|
break;
|
|
|
|
case INST_STSWI:
|
|
|
|
case INST_STSWX:
|
|
|
|
val = regs->gpr[rT] >> shift;
|
|
|
|
if (put_user(val, (u8 __user *)EA))
|
|
|
|
return -EFAULT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* move EA to next address */
|
|
|
|
EA += 1;
|
|
|
|
num_bytes--;
|
|
|
|
|
|
|
|
/* manage our position within the register */
|
|
|
|
if (++pos == 4) {
|
|
|
|
pos = 0;
|
|
|
|
if (++rT == 32)
|
|
|
|
rT = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int emulate_instruction(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
u32 instword;
|
|
|
|
u32 rd;
|
|
|
|
|
|
|
|
if (!user_mode(regs))
|
|
|
|
return -EINVAL;
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
|
|
|
if (get_user(instword, (u32 __user *)(regs->nip)))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
/* Emulate the mfspr rD, PVR.
|
|
|
|
*/
|
|
|
|
if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
|
|
|
|
rd = (instword >> 21) & 0x1f;
|
|
|
|
regs->gpr[rd] = mfspr(SPRN_PVR);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Emulating the dcba insn is just a no-op. */
|
|
|
|
if ((instword & INST_DCBA_MASK) == INST_DCBA)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Emulate the mcrxr insn. */
|
|
|
|
if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
|
|
|
|
int shift = (instword >> 21) & 0x1c;
|
|
|
|
unsigned long msk = 0xf0000000UL >> shift;
|
|
|
|
|
|
|
|
regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
|
|
|
|
regs->xer &= ~0xf0000000UL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Emulate load/store string insn. */
|
|
|
|
if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
|
|
|
|
return emulate_string_inst(regs, instword);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* After we have successfully emulated an instruction, we have to
|
|
|
|
* check if the instruction was being single-stepped, and if so,
|
|
|
|
* pretend we got a single-step exception. This was pointed out
|
|
|
|
* by Kumar Gala. -- paulus
|
|
|
|
*/
|
|
|
|
static void emulate_single_step(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
if (single_stepping(regs)) {
|
|
|
|
clear_single_step(regs);
|
|
|
|
_exception(SIGTRAP, regs, TRAP_TRACE, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Look through the list of trap instructions that are used for BUG(),
|
|
|
|
* BUG_ON() and WARN_ON() and see if we hit one. At this point we know
|
|
|
|
* that the exception was caused by a trap instruction of some kind.
|
|
|
|
* Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
|
|
|
|
* otherwise.
|
|
|
|
*/
|
|
|
|
extern struct bug_entry __start___bug_table[], __stop___bug_table[];
|
|
|
|
|
|
|
|
#ifndef CONFIG_MODULES
|
|
|
|
#define module_find_bug(x) NULL
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct bug_entry *find_bug(unsigned long bugaddr)
|
|
|
|
{
|
|
|
|
struct bug_entry *bug;
|
|
|
|
|
|
|
|
for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
|
|
|
|
if (bugaddr == bug->bug_addr)
|
|
|
|
return bug;
|
|
|
|
return module_find_bug(bugaddr);
|
|
|
|
}
|
|
|
|
|
|
|
|
int check_bug_trap(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
struct bug_entry *bug;
|
|
|
|
unsigned long addr;
|
|
|
|
|
|
|
|
if (regs->msr & MSR_PR)
|
|
|
|
return 0; /* not in kernel */
|
|
|
|
addr = regs->nip; /* address of trap instruction */
|
|
|
|
if (addr < PAGE_OFFSET)
|
|
|
|
return 0;
|
|
|
|
bug = find_bug(regs->nip);
|
|
|
|
if (bug == NULL)
|
|
|
|
return 0;
|
|
|
|
if (bug->line & BUG_WARNING_TRAP) {
|
|
|
|
/* this is a WARN_ON rather than BUG/BUG_ON */
|
|
|
|
#ifdef CONFIG_XMON
|
|
|
|
xmon_printf(KERN_ERR "Badness in %s at %s:%d\n",
|
|
|
|
bug->function, bug->file,
|
|
|
|
bug->line & ~BUG_WARNING_TRAP);
|
|
|
|
#endif /* CONFIG_XMON */
|
|
|
|
printk(KERN_ERR "Badness in %s at %s:%d\n",
|
|
|
|
bug->function, bug->file,
|
|
|
|
bug->line & ~BUG_WARNING_TRAP);
|
|
|
|
dump_stack();
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_XMON
|
|
|
|
xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
|
|
|
|
bug->function, bug->file, bug->line);
|
|
|
|
xmon(regs);
|
|
|
|
#endif /* CONFIG_XMON */
|
|
|
|
printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
|
|
|
|
bug->function, bug->file, bug->line);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProgramCheckException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
unsigned int reason = get_reason(regs);
|
|
|
|
extern int do_mathemu(struct pt_regs *regs);
|
|
|
|
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
|
|
/* (reason & REASON_ILLEGAL) would be the obvious thing here,
|
|
|
|
* but there seems to be a hardware bug on the 405GP (RevD)
|
|
|
|
* that means ESR is sometimes set incorrectly - either to
|
|
|
|
* ESR_DST (!?) or 0. In the process of chasing this with the
|
|
|
|
* hardware people - not sure if it can happen on any illegal
|
|
|
|
* instruction or only on FP instructions, whether there is a
|
|
|
|
* pattern to occurences etc. -dgibson 31/Mar/2003 */
|
|
|
|
if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
|
|
|
|
emulate_single_step(regs);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_MATH_EMULATION */
|
|
|
|
|
|
|
|
if (reason & REASON_FP) {
|
|
|
|
/* IEEE FP exception */
|
|
|
|
int code = 0;
|
|
|
|
u32 fpscr;
|
|
|
|
|
|
|
|
/* We must make sure the FP state is consistent with
|
|
|
|
* our MSR_FP in regs
|
|
|
|
*/
|
|
|
|
preempt_disable();
|
|
|
|
if (regs->msr & MSR_FP)
|
|
|
|
giveup_fpu(current);
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
fpscr = current->thread.fpscr;
|
|
|
|
fpscr &= fpscr << 22; /* mask summary bits with enables */
|
|
|
|
if (fpscr & FPSCR_VX)
|
|
|
|
code = FPE_FLTINV;
|
|
|
|
else if (fpscr & FPSCR_OX)
|
|
|
|
code = FPE_FLTOVF;
|
|
|
|
else if (fpscr & FPSCR_UX)
|
|
|
|
code = FPE_FLTUND;
|
|
|
|
else if (fpscr & FPSCR_ZX)
|
|
|
|
code = FPE_FLTDIV;
|
|
|
|
else if (fpscr & FPSCR_XX)
|
|
|
|
code = FPE_FLTRES;
|
|
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reason & REASON_TRAP) {
|
|
|
|
/* trap exception */
|
|
|
|
if (debugger_bpt(regs))
|
|
|
|
return;
|
|
|
|
if (check_bug_trap(regs)) {
|
|
|
|
regs->nip += 4;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
_exception(SIGTRAP, regs, TRAP_BRKPT, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Try to emulate it if we should. */
|
|
|
|
if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
|
|
|
|
switch (emulate_instruction(regs)) {
|
|
|
|
case 0:
|
|
|
|
regs->nip += 4;
|
|
|
|
emulate_single_step(regs);
|
|
|
|
return;
|
|
|
|
case -EFAULT:
|
|
|
|
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reason & REASON_PRIVILEGED)
|
|
|
|
_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
|
|
|
|
else
|
|
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
|
|
}
|
|
|
|
|
|
|
|
void SingleStepException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
|
|
|
|
if (debugger_sstep(regs))
|
|
|
|
return;
|
|
|
|
_exception(SIGTRAP, regs, TRAP_TRACE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void AlignmentException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
int fixed;
|
|
|
|
|
|
|
|
fixed = fix_alignment(regs);
|
|
|
|
if (fixed == 1) {
|
|
|
|
regs->nip += 4; /* skip over emulated instruction */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (fixed == -EFAULT) {
|
|
|
|
/* fixed == -EFAULT means the operand address was bad */
|
|
|
|
if (user_mode(regs))
|
|
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
|
|
|
|
else
|
|
|
|
bad_page_fault(regs, regs->dar, SIGSEGV);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
_exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
|
|
|
|
}
|
|
|
|
|
|
|
|
void StackOverflow(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
|
|
|
|
current, regs->gpr[1]);
|
|
|
|
debugger(regs);
|
|
|
|
show_regs(regs);
|
|
|
|
panic("kernel stack overflow");
|
|
|
|
}
|
|
|
|
|
|
|
|
void nonrecoverable_exception(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
|
|
|
|
regs->nip, regs->msr);
|
|
|
|
debugger(regs);
|
|
|
|
die("nonrecoverable exception", regs, SIGKILL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void trace_syscall(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
|
|
|
|
current, current->pid, regs->nip, regs->link, regs->gpr[0],
|
|
|
|
regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_8xx
|
|
|
|
void SoftwareEmulation(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
extern int do_mathemu(struct pt_regs *);
|
|
|
|
extern int Soft_emulate_8xx(struct pt_regs *);
|
|
|
|
int errcode;
|
|
|
|
|
|
|
|
CHECK_FULL_REGS(regs);
|
|
|
|
|
|
|
|
if (!user_mode(regs)) {
|
|
|
|
debugger(regs);
|
|
|
|
die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_MATH_EMULATION
|
|
|
|
errcode = do_mathemu(regs);
|
|
|
|
#else
|
|
|
|
errcode = Soft_emulate_8xx(regs);
|
|
|
|
#endif
|
|
|
|
if (errcode) {
|
|
|
|
if (errcode > 0)
|
|
|
|
_exception(SIGFPE, regs, 0, 0);
|
|
|
|
else if (errcode == -EFAULT)
|
|
|
|
_exception(SIGSEGV, regs, 0, 0);
|
|
|
|
else
|
|
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
|
|
} else
|
|
|
|
emulate_single_step(regs);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_8xx */
|
|
|
|
|
|
|
|
#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
|
|
|
|
|
|
|
|
void DebugException(struct pt_regs *regs, unsigned long debug_status)
|
|
|
|
{
|
|
|
|
if (debug_status & DBSR_IC) { /* instruction completion */
|
|
|
|
regs->msr &= ~MSR_DE;
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
current->thread.dbcr0 &= ~DBCR0_IC;
|
|
|
|
} else {
|
|
|
|
/* Disable instruction completion */
|
|
|
|
mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
|
|
|
|
/* Clear the instruction completion event */
|
|
|
|
mtspr(SPRN_DBSR, DBSR_IC);
|
|
|
|
if (debugger_sstep(regs))
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
_exception(SIGTRAP, regs, TRAP_TRACE, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_4xx || CONFIG_BOOKE */
|
|
|
|
|
|
|
|
#if !defined(CONFIG_TAU_INT)
|
|
|
|
void TAUException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
|
|
|
|
regs->nip, regs->msr, regs->trap, print_tainted());
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_INT_TAU */
|
|
|
|
|
|
|
|
void AltivecUnavailException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
static int kernel_altivec_count;
|
|
|
|
|
|
|
|
#ifndef CONFIG_ALTIVEC
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
/* A user program has executed an altivec instruction,
|
|
|
|
but this kernel doesn't support altivec. */
|
|
|
|
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* The kernel has executed an altivec instruction without
|
|
|
|
first enabling altivec. Whinge but let it do it. */
|
|
|
|
if (++kernel_altivec_count < 10)
|
|
|
|
printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
|
|
|
|
current, regs->nip);
|
|
|
|
regs->msr |= MSR_VEC;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
void AltivecAssistException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
preempt_disable();
|
|
|
|
if (regs->msr & MSR_VEC)
|
|
|
|
giveup_altivec(current);
|
|
|
|
preempt_enable();
|
2005-04-17 05:24:17 +07:00
|
|
|
if (!user_mode(regs)) {
|
|
|
|
printk(KERN_ERR "altivec assist exception in kernel mode"
|
|
|
|
" at %lx\n", regs->nip);
|
|
|
|
debugger(regs);
|
|
|
|
die("altivec assist exception", regs, SIGFPE);
|
|
|
|
return;
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
err = emulate_altivec(regs);
|
|
|
|
if (err == 0) {
|
|
|
|
regs->nip += 4; /* skip emulated instruction */
|
|
|
|
emulate_single_step(regs);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err == -EFAULT) {
|
|
|
|
/* got an error reading the instruction */
|
|
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
|
|
|
|
} else {
|
|
|
|
/* didn't recognize the instruction */
|
|
|
|
/* XXX quick hack for now: set the non-Java bit in the VSCR */
|
|
|
|
printk(KERN_ERR "unrecognized altivec instruction "
|
|
|
|
"in %s at %lx\n", current->comm, regs->nip);
|
|
|
|
current->thread.vscr.u[3] |= 0x10000;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
|
|
|
void PerformanceMonitorException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
perf_irq(regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_BOOKE
|
|
|
|
void CacheLockingException(struct pt_regs *regs, unsigned long address,
|
|
|
|
unsigned long error_code)
|
|
|
|
{
|
|
|
|
/* We treat cache locking instructions from the user
|
|
|
|
* as priv ops, in the future we could try to do
|
|
|
|
* something smarter
|
|
|
|
*/
|
|
|
|
if (error_code & (ESR_DLK|ESR_ILK))
|
|
|
|
_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_FSL_BOOKE */
|
|
|
|
|
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
void SPEFloatingPointException(struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
unsigned long spefscr;
|
|
|
|
int fpexc_mode;
|
|
|
|
int code = 0;
|
|
|
|
|
|
|
|
spefscr = current->thread.spefscr;
|
|
|
|
fpexc_mode = current->thread.fpexc_mode;
|
|
|
|
|
|
|
|
/* Hardware does not neccessarily set sticky
|
|
|
|
* underflow/overflow/invalid flags */
|
|
|
|
if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
|
|
|
|
code = FPE_FLTOVF;
|
|
|
|
spefscr |= SPEFSCR_FOVFS;
|
|
|
|
}
|
|
|
|
else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
|
|
|
|
code = FPE_FLTUND;
|
|
|
|
spefscr |= SPEFSCR_FUNFS;
|
|
|
|
}
|
|
|
|
else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
|
|
|
|
code = FPE_FLTDIV;
|
|
|
|
else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
|
|
|
|
code = FPE_FLTINV;
|
|
|
|
spefscr |= SPEFSCR_FINVS;
|
|
|
|
}
|
|
|
|
else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
|
|
|
|
code = FPE_FLTRES;
|
|
|
|
|
|
|
|
current->thread.spefscr = spefscr;
|
|
|
|
|
|
|
|
_exception(SIGFPE, regs, code, regs->nip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void __init trap_init(void)
|
|
|
|
{
|
|
|
|
}
|