mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 21:36:44 +07:00
806 lines
21 KiB
C
806 lines
21 KiB
C
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/* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro
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*
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* Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Thomas Hellstrom.
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* Partially based on code obtained from Digeo Inc.
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*/
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/*
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* Unmaps the DMA mappings.
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* FIXME: Is this a NoOp on x86? Also
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* FIXME: What happens if this one is called and a pending blit has previously done
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* the same DMA mappings?
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*/
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#include "drmP.h"
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#include "via_drm.h"
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#include "via_drv.h"
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#include "via_dmablit.h"
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#include <linux/pagemap.h>
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#define VIA_PGDN(x) (((unsigned long)(x)) & PAGE_MASK)
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#define VIA_PGOFF(x) (((unsigned long)(x)) & ~PAGE_MASK)
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#define VIA_PFN(x) ((unsigned long)(x) >> PAGE_SHIFT)
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typedef struct _drm_via_descriptor {
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uint32_t mem_addr;
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uint32_t dev_addr;
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uint32_t size;
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uint32_t next;
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} drm_via_descriptor_t;
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/*
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* Unmap a DMA mapping.
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*/
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static void
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via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
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{
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int num_desc = vsg->num_desc;
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unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page;
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unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page;
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drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] +
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descriptor_this_page;
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dma_addr_t next = vsg->chain_start;
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while(num_desc--) {
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if (descriptor_this_page-- == 0) {
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cur_descriptor_page--;
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descriptor_this_page = vsg->descriptors_per_page - 1;
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desc_ptr = vsg->desc_pages[cur_descriptor_page] +
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descriptor_this_page;
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}
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dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE);
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dma_unmap_page(&pdev->dev, desc_ptr->mem_addr, desc_ptr->size, vsg->direction);
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next = (dma_addr_t) desc_ptr->next;
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desc_ptr--;
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}
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}
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/*
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* If mode = 0, count how many descriptors are needed.
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* If mode = 1, Map the DMA pages for the device, put together and map also the descriptors.
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* Descriptors are run in reverse order by the hardware because we are not allowed to update the
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* 'next' field without syncing calls when the descriptor is already mapped.
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*/
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static void
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via_map_blit_for_device(struct pci_dev *pdev,
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const drm_via_dmablit_t *xfer,
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drm_via_sg_info_t *vsg,
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int mode)
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{
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unsigned cur_descriptor_page = 0;
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unsigned num_descriptors_this_page = 0;
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unsigned char *mem_addr = xfer->mem_addr;
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unsigned char *cur_mem;
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unsigned char *first_addr = (unsigned char *)VIA_PGDN(mem_addr);
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uint32_t fb_addr = xfer->fb_addr;
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uint32_t cur_fb;
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unsigned long line_len;
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unsigned remaining_len;
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int num_desc = 0;
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int cur_line;
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dma_addr_t next = 0 | VIA_DMA_DPR_EC;
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drm_via_descriptor_t *desc_ptr = 0;
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if (mode == 1)
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desc_ptr = vsg->desc_pages[cur_descriptor_page];
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for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) {
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line_len = xfer->line_length;
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cur_fb = fb_addr;
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cur_mem = mem_addr;
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while (line_len > 0) {
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remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len);
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line_len -= remaining_len;
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if (mode == 1) {
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desc_ptr->mem_addr =
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dma_map_page(&pdev->dev,
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vsg->pages[VIA_PFN(cur_mem) -
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VIA_PFN(first_addr)],
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VIA_PGOFF(cur_mem), remaining_len,
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vsg->direction);
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desc_ptr->dev_addr = cur_fb;
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desc_ptr->size = remaining_len;
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desc_ptr->next = (uint32_t) next;
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next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr),
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DMA_TO_DEVICE);
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desc_ptr++;
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if (++num_descriptors_this_page >= vsg->descriptors_per_page) {
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num_descriptors_this_page = 0;
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desc_ptr = vsg->desc_pages[++cur_descriptor_page];
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}
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}
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num_desc++;
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cur_mem += remaining_len;
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cur_fb += remaining_len;
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}
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mem_addr += xfer->mem_stride;
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fb_addr += xfer->fb_stride;
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}
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if (mode == 1) {
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vsg->chain_start = next;
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vsg->state = dr_via_device_mapped;
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}
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vsg->num_desc = num_desc;
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}
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/*
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* Function that frees up all resources for a blit. It is usable even if the
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* blit info has only be partially built as long as the status enum is consistent
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* with the actual status of the used resources.
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*/
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void
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via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
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{
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struct page *page;
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int i;
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switch(vsg->state) {
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case dr_via_device_mapped:
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via_unmap_blit_from_device(pdev, vsg);
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case dr_via_desc_pages_alloc:
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for (i=0; i<vsg->num_desc_pages; ++i) {
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if (vsg->desc_pages[i] != NULL)
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free_page((unsigned long)vsg->desc_pages[i]);
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}
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kfree(vsg->desc_pages);
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case dr_via_pages_locked:
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for (i=0; i<vsg->num_pages; ++i) {
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if ( NULL != (page = vsg->pages[i])) {
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if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction))
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SetPageDirty(page);
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page_cache_release(page);
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}
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}
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case dr_via_pages_alloc:
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vfree(vsg->pages);
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default:
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vsg->state = dr_via_sg_init;
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}
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if (vsg->bounce_buffer) {
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vfree(vsg->bounce_buffer);
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vsg->bounce_buffer = NULL;
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}
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vsg->free_on_sequence = 0;
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}
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/*
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* Fire a blit engine.
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*/
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static void
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via_fire_dmablit(drm_device_t *dev, drm_via_sg_info_t *vsg, int engine)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
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VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
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VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
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VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
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VIA_DMA_CSR_DE);
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VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
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VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
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VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
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VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
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}
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/*
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* Obtain a page pointer array and lock all pages into system memory. A segmentation violation will
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* occur here if the calling user does not have access to the submitted address.
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*/
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static int
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via_lock_all_dma_pages(drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
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{
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int ret;
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unsigned long first_pfn = VIA_PFN(xfer->mem_addr);
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vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) -
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first_pfn + 1;
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if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages)))
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return DRM_ERR(ENOMEM);
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memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
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down_read(¤t->mm->mmap_sem);
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ret = get_user_pages(current, current->mm, (unsigned long) xfer->mem_addr,
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vsg->num_pages, vsg->direction, 0, vsg->pages, NULL);
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up_read(¤t->mm->mmap_sem);
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if (ret != vsg->num_pages) {
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if (ret < 0)
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return ret;
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vsg->state = dr_via_pages_locked;
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return DRM_ERR(EINVAL);
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}
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vsg->state = dr_via_pages_locked;
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DRM_DEBUG("DMA pages locked\n");
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return 0;
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}
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/*
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* Allocate DMA capable memory for the blit descriptor chain, and an array that keeps track of the
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* pages we allocate. We don't want to use kmalloc for the descriptor chain because it may be
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* quite large for some blits, and pages don't need to be contingous.
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*/
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static int
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via_alloc_desc_pages(drm_via_sg_info_t *vsg)
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{
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int i;
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vsg->descriptors_per_page = PAGE_SIZE / sizeof( drm_via_descriptor_t);
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vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) /
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vsg->descriptors_per_page;
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if (NULL == (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL)))
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return DRM_ERR(ENOMEM);
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memset(vsg->desc_pages, 0, sizeof(void *) * vsg->num_desc_pages);
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vsg->state = dr_via_desc_pages_alloc;
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for (i=0; i<vsg->num_desc_pages; ++i) {
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if (NULL == (vsg->desc_pages[i] =
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(drm_via_descriptor_t *) __get_free_page(GFP_KERNEL)))
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return DRM_ERR(ENOMEM);
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}
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DRM_DEBUG("Allocated %d pages for %d descriptors.\n", vsg->num_desc_pages,
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vsg->num_desc);
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return 0;
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}
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static void
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via_abort_dmablit(drm_device_t *dev, int engine)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
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VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
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}
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static void
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via_dmablit_engine_off(drm_device_t *dev, int engine)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
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VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
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}
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/*
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* The dmablit part of the IRQ handler. Trying to do only reasonably fast things here.
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* The rest, like unmapping and freeing memory for done blits is done in a separate workqueue
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* task. Basically the task of the interrupt handler is to submit a new blit to the engine, while
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* the workqueue task takes care of processing associated with the old blit.
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*/
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void
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via_dmablit_handler(drm_device_t *dev, int engine, int from_irq)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
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drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
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int cur;
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int done_transfer;
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unsigned long irqsave=0;
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uint32_t status = 0;
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DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n",
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engine, from_irq, (unsigned long) blitq);
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if (from_irq) {
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spin_lock(&blitq->blit_lock);
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} else {
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spin_lock_irqsave(&blitq->blit_lock, irqsave);
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}
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done_transfer = blitq->is_active &&
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(( status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
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done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE));
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cur = blitq->cur;
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if (done_transfer) {
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blitq->blits[cur]->aborted = blitq->aborting;
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blitq->done_blit_handle++;
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DRM_WAKEUP(blitq->blit_queue + cur);
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cur++;
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if (cur >= VIA_NUM_BLIT_SLOTS)
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cur = 0;
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blitq->cur = cur;
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/*
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* Clear transfer done flag.
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*/
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VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD);
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blitq->is_active = 0;
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blitq->aborting = 0;
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schedule_work(&blitq->wq);
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} else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) {
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/*
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* Abort transfer after one second.
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*/
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via_abort_dmablit(dev, engine);
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blitq->aborting = 1;
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blitq->end = jiffies + DRM_HZ;
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}
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if (!blitq->is_active) {
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if (blitq->num_outstanding) {
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via_fire_dmablit(dev, blitq->blits[cur], engine);
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blitq->is_active = 1;
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blitq->cur = cur;
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blitq->num_outstanding--;
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blitq->end = jiffies + DRM_HZ;
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if (!timer_pending(&blitq->poll_timer)) {
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blitq->poll_timer.expires = jiffies+1;
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add_timer(&blitq->poll_timer);
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}
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} else {
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if (timer_pending(&blitq->poll_timer)) {
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del_timer(&blitq->poll_timer);
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}
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via_dmablit_engine_off(dev, engine);
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}
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}
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if (from_irq) {
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spin_unlock(&blitq->blit_lock);
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} else {
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spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
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}
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}
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/*
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* Check whether this blit is still active, performing necessary locking.
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*/
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static int
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||
|
via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue)
|
||
|
{
|
||
|
unsigned long irqsave;
|
||
|
uint32_t slot;
|
||
|
int active;
|
||
|
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
/*
|
||
|
* Allow for handle wraparounds.
|
||
|
*/
|
||
|
|
||
|
active = ((blitq->done_blit_handle - handle) > (1 << 23)) &&
|
||
|
((blitq->cur_blit_handle - handle) <= (1 << 23));
|
||
|
|
||
|
if (queue && active) {
|
||
|
slot = handle - blitq->done_blit_handle + blitq->cur -1;
|
||
|
if (slot >= VIA_NUM_BLIT_SLOTS) {
|
||
|
slot -= VIA_NUM_BLIT_SLOTS;
|
||
|
}
|
||
|
*queue = blitq->blit_queue + slot;
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
return active;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Sync. Wait for at least three seconds for the blit to be performed.
|
||
|
*/
|
||
|
|
||
|
static int
|
||
|
via_dmablit_sync(drm_device_t *dev, uint32_t handle, int engine)
|
||
|
{
|
||
|
|
||
|
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
|
||
|
drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
|
||
|
wait_queue_head_t *queue;
|
||
|
int ret = 0;
|
||
|
|
||
|
if (via_dmablit_active(blitq, engine, handle, &queue)) {
|
||
|
DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ,
|
||
|
!via_dmablit_active(blitq, engine, handle, NULL));
|
||
|
}
|
||
|
DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n",
|
||
|
handle, engine, ret);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
|
||
|
/*
|
||
|
* A timer that regularly polls the blit engine in cases where we don't have interrupts:
|
||
|
* a) Broken hardware (typically those that don't have any video capture facility).
|
||
|
* b) Blit abort. The hardware doesn't send an interrupt when a blit is aborted.
|
||
|
* The timer and hardware IRQ's can and do work in parallel. If the hardware has
|
||
|
* irqs, it will shorten the latency somewhat.
|
||
|
*/
|
||
|
|
||
|
|
||
|
|
||
|
static void
|
||
|
via_dmablit_timer(unsigned long data)
|
||
|
{
|
||
|
drm_via_blitq_t *blitq = (drm_via_blitq_t *) data;
|
||
|
drm_device_t *dev = blitq->dev;
|
||
|
int engine = (int)
|
||
|
(blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues);
|
||
|
|
||
|
DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine,
|
||
|
(unsigned long) jiffies);
|
||
|
|
||
|
via_dmablit_handler(dev, engine, 0);
|
||
|
|
||
|
if (!timer_pending(&blitq->poll_timer)) {
|
||
|
blitq->poll_timer.expires = jiffies+1;
|
||
|
add_timer(&blitq->poll_timer);
|
||
|
}
|
||
|
via_dmablit_handler(dev, engine, 0);
|
||
|
|
||
|
}
|
||
|
|
||
|
|
||
|
|
||
|
|
||
|
/*
|
||
|
* Workqueue task that frees data and mappings associated with a blit.
|
||
|
* Also wakes up waiting processes. Each of these tasks handles one
|
||
|
* blit engine only and may not be called on each interrupt.
|
||
|
*/
|
||
|
|
||
|
|
||
|
static void
|
||
|
via_dmablit_workqueue(void *data)
|
||
|
{
|
||
|
drm_via_blitq_t *blitq = (drm_via_blitq_t *) data;
|
||
|
drm_device_t *dev = blitq->dev;
|
||
|
unsigned long irqsave;
|
||
|
drm_via_sg_info_t *cur_sg;
|
||
|
int cur_released;
|
||
|
|
||
|
|
||
|
DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long)
|
||
|
(blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues));
|
||
|
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
while(blitq->serviced != blitq->cur) {
|
||
|
|
||
|
cur_released = blitq->serviced++;
|
||
|
|
||
|
DRM_DEBUG("Releasing blit slot %d\n", cur_released);
|
||
|
|
||
|
if (blitq->serviced >= VIA_NUM_BLIT_SLOTS)
|
||
|
blitq->serviced = 0;
|
||
|
|
||
|
cur_sg = blitq->blits[cur_released];
|
||
|
blitq->num_free++;
|
||
|
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
DRM_WAKEUP(&blitq->busy_queue);
|
||
|
|
||
|
via_free_sg_info(dev->pdev, cur_sg);
|
||
|
kfree(cur_sg);
|
||
|
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
}
|
||
|
|
||
|
|
||
|
/*
|
||
|
* Init all blit engines. Currently we use two, but some hardware have 4.
|
||
|
*/
|
||
|
|
||
|
|
||
|
void
|
||
|
via_init_dmablit(drm_device_t *dev)
|
||
|
{
|
||
|
int i,j;
|
||
|
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
|
||
|
drm_via_blitq_t *blitq;
|
||
|
|
||
|
pci_set_master(dev->pdev);
|
||
|
|
||
|
for (i=0; i< VIA_NUM_BLIT_ENGINES; ++i) {
|
||
|
blitq = dev_priv->blit_queues + i;
|
||
|
blitq->dev = dev;
|
||
|
blitq->cur_blit_handle = 0;
|
||
|
blitq->done_blit_handle = 0;
|
||
|
blitq->head = 0;
|
||
|
blitq->cur = 0;
|
||
|
blitq->serviced = 0;
|
||
|
blitq->num_free = VIA_NUM_BLIT_SLOTS;
|
||
|
blitq->num_outstanding = 0;
|
||
|
blitq->is_active = 0;
|
||
|
blitq->aborting = 0;
|
||
|
blitq->blit_lock = SPIN_LOCK_UNLOCKED;
|
||
|
for (j=0; j<VIA_NUM_BLIT_SLOTS; ++j) {
|
||
|
DRM_INIT_WAITQUEUE(blitq->blit_queue + j);
|
||
|
}
|
||
|
DRM_INIT_WAITQUEUE(&blitq->busy_queue);
|
||
|
INIT_WORK(&blitq->wq, via_dmablit_workqueue, blitq);
|
||
|
init_timer(&blitq->poll_timer);
|
||
|
blitq->poll_timer.function = &via_dmablit_timer;
|
||
|
blitq->poll_timer.data = (unsigned long) blitq;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Build all info and do all mappings required for a blit.
|
||
|
*/
|
||
|
|
||
|
|
||
|
static int
|
||
|
via_build_sg_info(drm_device_t *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
|
||
|
{
|
||
|
int draw = xfer->to_fb;
|
||
|
int ret = 0;
|
||
|
|
||
|
vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
|
||
|
vsg->bounce_buffer = 0;
|
||
|
|
||
|
vsg->state = dr_via_sg_init;
|
||
|
|
||
|
if (xfer->num_lines <= 0 || xfer->line_length <= 0) {
|
||
|
DRM_ERROR("Zero size bitblt.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Below check is a driver limitation, not a hardware one. We
|
||
|
* don't want to lock unused pages, and don't want to incoporate the
|
||
|
* extra logic of avoiding them. Make sure there are no.
|
||
|
* (Not a big limitation anyway.)
|
||
|
*/
|
||
|
|
||
|
if (((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) ||
|
||
|
(xfer->mem_stride > 2048*4)) {
|
||
|
DRM_ERROR("Too large system memory stride. Stride: %d, "
|
||
|
"Length: %d\n", xfer->mem_stride, xfer->line_length);
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
|
||
|
if (xfer->num_lines > 2048) {
|
||
|
DRM_ERROR("Too many PCI DMA bitblt lines.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* we allow a negative fb stride to allow flipping of images in
|
||
|
* transfer.
|
||
|
*/
|
||
|
|
||
|
if (xfer->mem_stride < xfer->line_length ||
|
||
|
abs(xfer->fb_stride) < xfer->line_length) {
|
||
|
DRM_ERROR("Invalid frame-buffer / memory stride.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* A hardware bug seems to be worked around if system memory addresses start on
|
||
|
* 16 byte boundaries. This seems a bit restrictive however. VIA is contacted
|
||
|
* about this. Meanwhile, impose the following restrictions:
|
||
|
*/
|
||
|
|
||
|
#ifdef VIA_BUGFREE
|
||
|
if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) ||
|
||
|
((xfer->mem_stride & 3) != (xfer->fb_stride & 3))) {
|
||
|
DRM_ERROR("Invalid DRM bitblt alignment.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
#else
|
||
|
if ((((unsigned long)xfer->mem_addr & 15) ||
|
||
|
((unsigned long)xfer->fb_addr & 3)) || (xfer->mem_stride & 15) ||
|
||
|
(xfer->fb_stride & 3)) {
|
||
|
DRM_ERROR("Invalid DRM bitblt alignment.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
#endif
|
||
|
|
||
|
if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) {
|
||
|
DRM_ERROR("Could not lock DMA pages.\n");
|
||
|
via_free_sg_info(dev->pdev, vsg);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
via_map_blit_for_device(dev->pdev, xfer, vsg, 0);
|
||
|
if (0 != (ret = via_alloc_desc_pages(vsg))) {
|
||
|
DRM_ERROR("Could not allocate DMA descriptor pages.\n");
|
||
|
via_free_sg_info(dev->pdev, vsg);
|
||
|
return ret;
|
||
|
}
|
||
|
via_map_blit_for_device(dev->pdev, xfer, vsg, 1);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
|
||
|
/*
|
||
|
* Reserve one free slot in the blit queue. Will wait for one second for one
|
||
|
* to become available. Otherwise -EBUSY is returned.
|
||
|
*/
|
||
|
|
||
|
static int
|
||
|
via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine)
|
||
|
{
|
||
|
int ret=0;
|
||
|
unsigned long irqsave;
|
||
|
|
||
|
DRM_DEBUG("Num free is %d\n", blitq->num_free);
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
while(blitq->num_free == 0) {
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
DRM_WAIT_ON(ret, blitq->busy_queue, DRM_HZ, blitq->num_free > 0);
|
||
|
if (ret) {
|
||
|
return (DRM_ERR(EINTR) == ret) ? DRM_ERR(EAGAIN) : ret;
|
||
|
}
|
||
|
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
}
|
||
|
|
||
|
blitq->num_free--;
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Hand back a free slot if we changed our mind.
|
||
|
*/
|
||
|
|
||
|
static void
|
||
|
via_dmablit_release_slot(drm_via_blitq_t *blitq)
|
||
|
{
|
||
|
unsigned long irqsave;
|
||
|
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
blitq->num_free++;
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
DRM_WAKEUP( &blitq->busy_queue );
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Grab a free slot. Build blit info and queue a blit.
|
||
|
*/
|
||
|
|
||
|
|
||
|
static int
|
||
|
via_dmablit(drm_device_t *dev, drm_via_dmablit_t *xfer)
|
||
|
{
|
||
|
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
|
||
|
drm_via_sg_info_t *vsg;
|
||
|
drm_via_blitq_t *blitq;
|
||
|
int ret;
|
||
|
int engine;
|
||
|
unsigned long irqsave;
|
||
|
|
||
|
if (dev_priv == NULL) {
|
||
|
DRM_ERROR("Called without initialization.\n");
|
||
|
return DRM_ERR(EINVAL);
|
||
|
}
|
||
|
|
||
|
engine = (xfer->to_fb) ? 0 : 1;
|
||
|
blitq = dev_priv->blit_queues + engine;
|
||
|
if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) {
|
||
|
return ret;
|
||
|
}
|
||
|
if (NULL == (vsg = kmalloc(sizeof(*vsg), GFP_KERNEL))) {
|
||
|
via_dmablit_release_slot(blitq);
|
||
|
return DRM_ERR(ENOMEM);
|
||
|
}
|
||
|
if (0 != (ret = via_build_sg_info(dev, vsg, xfer))) {
|
||
|
via_dmablit_release_slot(blitq);
|
||
|
kfree(vsg);
|
||
|
return ret;
|
||
|
}
|
||
|
spin_lock_irqsave(&blitq->blit_lock, irqsave);
|
||
|
|
||
|
blitq->blits[blitq->head++] = vsg;
|
||
|
if (blitq->head >= VIA_NUM_BLIT_SLOTS)
|
||
|
blitq->head = 0;
|
||
|
blitq->num_outstanding++;
|
||
|
xfer->sync.sync_handle = ++blitq->cur_blit_handle;
|
||
|
|
||
|
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
|
||
|
xfer->sync.engine = engine;
|
||
|
|
||
|
via_dmablit_handler(dev, engine, 0);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Sync on a previously submitted blit. Note that the X server use signals extensively, and
|
||
|
* that there is a very big proability that this IOCTL will be interrupted by a signal. In that
|
||
|
* case it returns with -EAGAIN for the signal to be delivered.
|
||
|
* The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock().
|
||
|
*/
|
||
|
|
||
|
int
|
||
|
via_dma_blit_sync( DRM_IOCTL_ARGS )
|
||
|
{
|
||
|
drm_via_blitsync_t sync;
|
||
|
int err;
|
||
|
DRM_DEVICE;
|
||
|
|
||
|
DRM_COPY_FROM_USER_IOCTL(sync, (drm_via_blitsync_t *)data, sizeof(sync));
|
||
|
|
||
|
if (sync.engine >= VIA_NUM_BLIT_ENGINES)
|
||
|
return DRM_ERR(EINVAL);
|
||
|
|
||
|
err = via_dmablit_sync(dev, sync.sync_handle, sync.engine);
|
||
|
|
||
|
if (DRM_ERR(EINTR) == err)
|
||
|
err = DRM_ERR(EAGAIN);
|
||
|
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
|
||
|
/*
|
||
|
* Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal
|
||
|
* while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should
|
||
|
* be reissued. See the above IOCTL code.
|
||
|
*/
|
||
|
|
||
|
int
|
||
|
via_dma_blit( DRM_IOCTL_ARGS )
|
||
|
{
|
||
|
drm_via_dmablit_t xfer;
|
||
|
int err;
|
||
|
DRM_DEVICE;
|
||
|
|
||
|
DRM_COPY_FROM_USER_IOCTL(xfer, (drm_via_dmablit_t __user *)data, sizeof(xfer));
|
||
|
|
||
|
err = via_dmablit(dev, &xfer);
|
||
|
|
||
|
DRM_COPY_TO_USER_IOCTL((void __user *)data, xfer, sizeof(xfer));
|
||
|
|
||
|
return err;
|
||
|
}
|