License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-17 05:20:36 +07:00
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/*
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* linux/arch/alpha/kernel/sys_dp264.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996, 1999 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Modified by Christopher C. Chimelis, 2001 to
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* add support for the addition of Shark to the
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* Tsunami family.
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*
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* Code supporting the DP264 (EV6+TSUNAMI).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_tsunami.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/* Note mask bit is true for ENABLED irqs. */
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static unsigned long cached_irq_mask;
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/* dp264 boards handle at max four CPUs */
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static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
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DEFINE_SPINLOCK(dp264_irq_lock);
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static void
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tsunami_update_irq_hw(unsigned long mask)
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{
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register tsunami_cchip *cchip = TSUNAMI_cchip;
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unsigned long isa_enable = 1UL << 55;
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register int bcpu = boot_cpuid;
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#ifdef CONFIG_SMP
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volatile unsigned long *dim0, *dim1, *dim2, *dim3;
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unsigned long mask0, mask1, mask2, mask3, dummy;
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mask &= ~isa_enable;
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mask0 = mask & cpu_irq_affinity[0];
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mask1 = mask & cpu_irq_affinity[1];
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mask2 = mask & cpu_irq_affinity[2];
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mask3 = mask & cpu_irq_affinity[3];
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if (bcpu == 0) mask0 |= isa_enable;
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else if (bcpu == 1) mask1 |= isa_enable;
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else if (bcpu == 2) mask2 |= isa_enable;
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else mask3 |= isa_enable;
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dim0 = &cchip->dim0.csr;
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dim1 = &cchip->dim1.csr;
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dim2 = &cchip->dim2.csr;
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dim3 = &cchip->dim3.csr;
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if (!cpu_possible(0)) dim0 = &dummy;
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if (!cpu_possible(1)) dim1 = &dummy;
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if (!cpu_possible(2)) dim2 = &dummy;
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if (!cpu_possible(3)) dim3 = &dummy;
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*dim0 = mask0;
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*dim1 = mask1;
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*dim2 = mask2;
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*dim3 = mask3;
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mb();
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*dim0;
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*dim1;
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*dim2;
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*dim3;
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#else
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volatile unsigned long *dimB;
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if (bcpu == 0) dimB = &cchip->dim0.csr;
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else if (bcpu == 1) dimB = &cchip->dim1.csr;
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else if (bcpu == 2) dimB = &cchip->dim2.csr;
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else dimB = &cchip->dim3.csr;
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*dimB = mask | isa_enable;
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mb();
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*dimB;
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#endif
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}
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static void
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2011-02-06 21:32:33 +07:00
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dp264_enable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cached_irq_mask |= 1UL << d->irq;
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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2011-02-06 21:32:33 +07:00
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dp264_disable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cached_irq_mask &= ~(1UL << d->irq);
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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2011-02-06 21:32:33 +07:00
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clipper_enable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cached_irq_mask |= 1UL << (d->irq - 16);
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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2011-02-06 21:32:33 +07:00
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clipper_disable_irq(struct irq_data *d)
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2005-04-17 05:20:36 +07:00
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{
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cached_irq_mask &= ~(1UL << (d->irq - 16));
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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}
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static void
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cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
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{
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int cpu;
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for (cpu = 0; cpu < 4; cpu++) {
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unsigned long aff = cpu_irq_affinity[cpu];
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2011-05-25 07:12:56 +07:00
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if (cpumask_test_cpu(cpu, &affinity))
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2005-04-17 05:20:36 +07:00
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aff |= 1UL << irq;
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else
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aff &= ~(1UL << irq);
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cpu_irq_affinity[cpu] = aff;
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}
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}
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2009-04-28 07:59:21 +07:00
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static int
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2011-02-06 21:32:33 +07:00
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dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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2005-04-17 05:20:36 +07:00
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cpu_set_irq_affinity(d->irq, *affinity);
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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2009-04-28 07:59:21 +07:00
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return 0;
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2005-04-17 05:20:36 +07:00
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}
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2009-04-28 07:59:21 +07:00
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static int
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2011-02-06 21:32:33 +07:00
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clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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2005-04-17 05:20:36 +07:00
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spin_lock(&dp264_irq_lock);
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2011-02-06 21:32:33 +07:00
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cpu_set_irq_affinity(d->irq - 16, *affinity);
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2005-04-17 05:20:36 +07:00
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tsunami_update_irq_hw(cached_irq_mask);
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spin_unlock(&dp264_irq_lock);
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2009-04-28 07:59:21 +07:00
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return 0;
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2005-04-17 05:20:36 +07:00
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}
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2009-06-17 05:33:25 +07:00
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static struct irq_chip dp264_irq_type = {
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2011-02-06 21:32:33 +07:00
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.name = "DP264",
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.irq_unmask = dp264_enable_irq,
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.irq_mask = dp264_disable_irq,
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.irq_mask_ack = dp264_disable_irq,
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.irq_set_affinity = dp264_set_affinity,
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2005-04-17 05:20:36 +07:00
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};
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2009-06-17 05:33:25 +07:00
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static struct irq_chip clipper_irq_type = {
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2011-02-06 21:32:33 +07:00
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.name = "CLIPPER",
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.irq_unmask = clipper_enable_irq,
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.irq_mask = clipper_disable_irq,
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.irq_mask_ack = clipper_disable_irq,
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.irq_set_affinity = clipper_set_affinity,
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2005-04-17 05:20:36 +07:00
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};
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static void
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2006-10-08 20:36:08 +07:00
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dp264_device_interrupt(unsigned long vector)
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2005-04-17 05:20:36 +07:00
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{
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unsigned long pld;
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unsigned int i;
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/* Read the interrupt summary register of TSUNAMI */
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pld = TSUNAMI_cchip->dir0.csr;
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i == 55)
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2006-10-08 20:36:08 +07:00
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isa_device_interrupt(vector);
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2005-04-17 05:20:36 +07:00
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else
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2006-10-08 20:37:32 +07:00
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handle_irq(16 + i);
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2005-04-17 05:20:36 +07:00
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}
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}
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static void
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2006-10-08 20:36:08 +07:00
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dp264_srm_device_interrupt(unsigned long vector)
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2005-04-17 05:20:36 +07:00
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* The SRM console reports PCI interrupts with a vector calculated by:
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*
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* 0x900 + (0x10 * DRIR-bit)
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*
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* So bit 16 shows up as IRQ 32, etc.
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*
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* On DP264/BRICK/MONET, we adjust it down by 16 because at least
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* that many of the low order bits of the DRIR are not used, and
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* so we don't count them.
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*/
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if (irq >= 32)
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irq -= 16;
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2006-10-08 20:37:32 +07:00
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handle_irq(irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2006-10-08 20:36:08 +07:00
|
|
|
clipper_srm_device_interrupt(unsigned long vector)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
|
|
irq = (vector - 0x800) >> 4;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The SRM console reports PCI interrupts with a vector calculated by:
|
|
|
|
|
*
|
|
|
|
|
* 0x900 + (0x10 * DRIR-bit)
|
|
|
|
|
*
|
|
|
|
|
* So bit 16 shows up as IRQ 32, etc.
|
|
|
|
|
*
|
|
|
|
|
* CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
|
|
|
|
|
* to scale down the vector reported, we just use it.
|
|
|
|
|
*
|
|
|
|
|
* Eg IRQ 24 is DRIR bit 8, etc, etc
|
|
|
|
|
*/
|
2006-10-08 20:37:32 +07:00
|
|
|
handle_irq(irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
2009-06-17 05:33:25 +07:00
|
|
|
init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
|
long i;
|
|
|
|
|
for (i = imin; i <= imax; ++i) {
|
2011-03-26 04:17:31 +07:00
|
|
|
irq_set_chip_and_handler(i, ops, handle_level_irq);
|
2011-02-06 21:32:33 +07:00
|
|
|
irq_set_status_flags(i, IRQ_LEVEL);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
dp264_init_irq(void)
|
|
|
|
|
{
|
|
|
|
|
outb(0, DMA1_RESET_REG);
|
|
|
|
|
outb(0, DMA2_RESET_REG);
|
|
|
|
|
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
|
|
|
|
|
outb(0, DMA2_MASK_REG);
|
|
|
|
|
|
|
|
|
|
if (alpha_using_srm)
|
|
|
|
|
alpha_mv.device_interrupt = dp264_srm_device_interrupt;
|
|
|
|
|
|
|
|
|
|
tsunami_update_irq_hw(0);
|
|
|
|
|
|
|
|
|
|
init_i8259a_irqs();
|
|
|
|
|
init_tsunami_irqs(&dp264_irq_type, 16, 47);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
clipper_init_irq(void)
|
|
|
|
|
{
|
|
|
|
|
outb(0, DMA1_RESET_REG);
|
|
|
|
|
outb(0, DMA2_RESET_REG);
|
|
|
|
|
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
|
|
|
|
|
outb(0, DMA2_MASK_REG);
|
|
|
|
|
|
|
|
|
|
if (alpha_using_srm)
|
|
|
|
|
alpha_mv.device_interrupt = clipper_srm_device_interrupt;
|
|
|
|
|
|
|
|
|
|
tsunami_update_irq_hw(0);
|
|
|
|
|
|
|
|
|
|
init_i8259a_irqs();
|
|
|
|
|
init_tsunami_irqs(&clipper_irq_type, 24, 63);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PCI Fixup configuration.
|
|
|
|
|
*
|
|
|
|
|
* Summary @ TSUNAMI_CSR_DIM0:
|
|
|
|
|
* Bit Meaning
|
|
|
|
|
* 0-17 Unused
|
|
|
|
|
*18 Interrupt SCSI B (Adaptec 7895 builtin)
|
|
|
|
|
*19 Interrupt SCSI A (Adaptec 7895 builtin)
|
|
|
|
|
*20 Interrupt Line D from slot 2 PCI0
|
|
|
|
|
*21 Interrupt Line C from slot 2 PCI0
|
|
|
|
|
*22 Interrupt Line B from slot 2 PCI0
|
|
|
|
|
*23 Interrupt Line A from slot 2 PCI0
|
|
|
|
|
*24 Interrupt Line D from slot 1 PCI0
|
|
|
|
|
*25 Interrupt Line C from slot 1 PCI0
|
|
|
|
|
*26 Interrupt Line B from slot 1 PCI0
|
|
|
|
|
*27 Interrupt Line A from slot 1 PCI0
|
|
|
|
|
*28 Interrupt Line D from slot 0 PCI0
|
|
|
|
|
*29 Interrupt Line C from slot 0 PCI0
|
|
|
|
|
*30 Interrupt Line B from slot 0 PCI0
|
|
|
|
|
*31 Interrupt Line A from slot 0 PCI0
|
|
|
|
|
*
|
|
|
|
|
*32 Interrupt Line D from slot 3 PCI1
|
|
|
|
|
*33 Interrupt Line C from slot 3 PCI1
|
|
|
|
|
*34 Interrupt Line B from slot 3 PCI1
|
|
|
|
|
*35 Interrupt Line A from slot 3 PCI1
|
|
|
|
|
*36 Interrupt Line D from slot 2 PCI1
|
|
|
|
|
*37 Interrupt Line C from slot 2 PCI1
|
|
|
|
|
*38 Interrupt Line B from slot 2 PCI1
|
|
|
|
|
*39 Interrupt Line A from slot 2 PCI1
|
|
|
|
|
*40 Interrupt Line D from slot 1 PCI1
|
|
|
|
|
*41 Interrupt Line C from slot 1 PCI1
|
|
|
|
|
*42 Interrupt Line B from slot 1 PCI1
|
|
|
|
|
*43 Interrupt Line A from slot 1 PCI1
|
|
|
|
|
*44 Interrupt Line D from slot 0 PCI1
|
|
|
|
|
*45 Interrupt Line C from slot 0 PCI1
|
|
|
|
|
*46 Interrupt Line B from slot 0 PCI1
|
|
|
|
|
*47 Interrupt Line A from slot 0 PCI1
|
|
|
|
|
*48-52 Unused
|
|
|
|
|
*53 PCI0 NMI (from Cypress)
|
|
|
|
|
*54 PCI0 SMI INT (from Cypress)
|
|
|
|
|
*55 PCI0 ISA Interrupt (from Cypress)
|
|
|
|
|
*56-60 Unused
|
|
|
|
|
*61 PCI1 Bus Error
|
|
|
|
|
*62 PCI0 Bus Error
|
|
|
|
|
*63 Reserved
|
|
|
|
|
*
|
|
|
|
|
* IdSel
|
|
|
|
|
* 5 Cypress Bridge I/O
|
|
|
|
|
* 6 SCSI Adaptec builtin
|
|
|
|
|
* 7 64 bit PCI option slot 0 (all busses)
|
|
|
|
|
* 8 64 bit PCI option slot 1 (all busses)
|
|
|
|
|
* 9 64 bit PCI option slot 2 (all busses)
|
|
|
|
|
* 10 64 bit PCI option slot 3 (not bus 0)
|
|
|
|
|
*/
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static int
|
2012-03-19 07:01:09 +07:00
|
|
|
isa_irq_fixup(const struct pci_dev *dev, int irq)
|
2005-09-19 21:55:51 +07:00
|
|
|
{
|
|
|
|
|
u8 irq8;
|
|
|
|
|
|
|
|
|
|
if (irq > 0)
|
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
|
|
/* This interrupt is routed via ISA bridge, so we'll
|
|
|
|
|
just have to trust whatever value the console might
|
|
|
|
|
have assigned. */
|
|
|
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
|
|
|
|
|
|
|
|
|
|
return irq8 & 0xf;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static int
|
2011-06-10 21:30:21 +07:00
|
|
|
dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2017-10-26 21:54:15 +07:00
|
|
|
static char irq_tab[6][5] = {
|
2005-04-17 05:20:36 +07:00
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
|
|
|
|
|
{ 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
|
|
|
|
|
{ 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
|
|
|
|
|
{ 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
|
|
|
|
|
{ 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
|
|
|
|
|
{ 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
|
|
|
|
|
};
|
|
|
|
|
const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
|
|
|
|
|
struct pci_controller *hose = dev->sysdata;
|
|
|
|
|
int irq = COMMON_TABLE_LOOKUP;
|
|
|
|
|
|
2005-09-19 21:55:51 +07:00
|
|
|
if (irq > 0)
|
2005-04-17 05:20:36 +07:00
|
|
|
irq += 16 * hose->index;
|
|
|
|
|
|
2005-09-19 21:55:51 +07:00
|
|
|
return isa_irq_fixup(dev, irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static int
|
2011-06-10 21:30:21 +07:00
|
|
|
monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2017-10-26 21:54:15 +07:00
|
|
|
static char irq_tab[13][5] = {
|
2005-04-17 05:20:36 +07:00
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 4 unused */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 5 unused */
|
|
|
|
|
{ 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
|
|
|
|
|
#if 1
|
|
|
|
|
{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
|
|
|
|
|
{ 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
|
|
|
|
|
#else
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 9 unused */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */
|
|
|
|
|
#endif
|
|
|
|
|
{ 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
|
|
|
|
|
{ 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
|
|
|
|
|
{ 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
|
|
|
|
|
{ 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
|
|
|
|
|
{ 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
|
|
|
|
|
};
|
|
|
|
|
const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
|
2005-09-19 21:55:51 +07:00
|
|
|
|
|
|
|
|
return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static u8
|
2005-04-17 05:20:36 +07:00
|
|
|
monet_swizzle(struct pci_dev *dev, u8 *pinp)
|
|
|
|
|
{
|
|
|
|
|
struct pci_controller *hose = dev->sysdata;
|
|
|
|
|
int slot, pin = *pinp;
|
|
|
|
|
|
|
|
|
|
if (!dev->bus->parent) {
|
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
}
|
|
|
|
|
/* Check for the built-in bridge on hose 1. */
|
|
|
|
|
else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
|
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
} else {
|
|
|
|
|
/* Must be a card-based bridge. */
|
|
|
|
|
do {
|
|
|
|
|
/* Check for built-in bridge on hose 1. */
|
|
|
|
|
if (hose->index == 1 &&
|
|
|
|
|
PCI_SLOT(dev->bus->self->devfn) == 8) {
|
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2008-12-10 06:12:07 +07:00
|
|
|
pin = pci_swizzle_interrupt_pin(dev, pin);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
/* Move up the chain of bridges. */
|
|
|
|
|
dev = dev->bus->self;
|
|
|
|
|
/* Slot of the next bridge. */
|
|
|
|
|
slot = PCI_SLOT(dev->devfn);
|
|
|
|
|
} while (dev->bus->self);
|
|
|
|
|
}
|
|
|
|
|
*pinp = pin;
|
|
|
|
|
return slot;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static int
|
2011-06-10 21:30:21 +07:00
|
|
|
webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2017-10-26 21:54:15 +07:00
|
|
|
static char irq_tab[13][5] = {
|
2005-04-17 05:20:36 +07:00
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8 unused */
|
|
|
|
|
{ 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 10 unused */
|
|
|
|
|
{ 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 12 unused */
|
|
|
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 13 unused */
|
|
|
|
|
{ 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
|
|
|
|
|
{ 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
|
|
|
|
|
{ 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
|
|
|
|
|
{ 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
|
|
|
|
|
};
|
|
|
|
|
const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
|
2005-09-19 21:55:51 +07:00
|
|
|
|
|
|
|
|
return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2017-10-26 21:54:15 +07:00
|
|
|
static int
|
2011-06-10 21:30:21 +07:00
|
|
|
clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2017-10-26 21:54:15 +07:00
|
|
|
static char irq_tab[7][5] = {
|
2005-04-17 05:20:36 +07:00
|
|
|
/*INT INTA INTB INTC INTD */
|
|
|
|
|
{ 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
|
|
|
|
|
{ 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
|
|
|
|
|
{ 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
|
|
|
|
|
{ 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
|
|
|
|
|
{ 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
|
|
|
|
|
{ 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
|
|
|
|
|
{ -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
|
|
|
|
|
};
|
|
|
|
|
const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
|
|
|
|
|
struct pci_controller *hose = dev->sysdata;
|
|
|
|
|
int irq = COMMON_TABLE_LOOKUP;
|
|
|
|
|
|
|
|
|
|
if (irq > 0)
|
|
|
|
|
irq += 16 * hose->index;
|
|
|
|
|
|
2005-09-19 21:55:51 +07:00
|
|
|
return isa_irq_fixup(dev, irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
dp264_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
common_init_pci();
|
|
|
|
|
SMC669_Init(0);
|
ALPHA: support graphics on non-zero PCI domains
This code replaces earlier and incomplete handling of graphics on non-zero PCI
domains (aka hoses or peer PCI buses).
An option (CONFIG_VGA_HOSE) is set TRUE if configuring a GENERIC kernel, or a
kernel for MARVEL, TITAN, or TSUNAMI machines, as these are the machines whose
SRM consoles are capable of configuring and handling graphics options on
non-zero hoses. All other machines have the option set FALSE.
A routine, "find_console_vga_hose()", is used to find the graphics device
which the machine's firmware believes is the console device, and it sets a
global (pci_vga_hose) for later use in managing access to the device. This is
called in "init_arch" on TITAN and TSUNAMI machines; MARVEL machines use a
custom version of this routine because of extra complexity.
A routine, "locate_and_init_vga()", is used to find the graphics device and
set a global (pci_vga_hose) for later use in managing access to the device, in
the case where "find_console_vga_hose" has failed.
Various adjustments are made to the ioremap and ioportmap routines for
detecting and translating "legacy" VGA register and memory references to the
real PCI domain.
[akpm@linux-foundation.org: don't statically init bss]
[akpm@linux-foundation.org: build fix]
Signed-off-by: Jay Estabrook <jay.estabrook@hp.com>
Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-06-01 14:47:03 +07:00
|
|
|
locate_and_init_vga(NULL);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
monet_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
common_init_pci();
|
|
|
|
|
SMC669_Init(1);
|
|
|
|
|
es1888_init();
|
ALPHA: support graphics on non-zero PCI domains
This code replaces earlier and incomplete handling of graphics on non-zero PCI
domains (aka hoses or peer PCI buses).
An option (CONFIG_VGA_HOSE) is set TRUE if configuring a GENERIC kernel, or a
kernel for MARVEL, TITAN, or TSUNAMI machines, as these are the machines whose
SRM consoles are capable of configuring and handling graphics options on
non-zero hoses. All other machines have the option set FALSE.
A routine, "find_console_vga_hose()", is used to find the graphics device
which the machine's firmware believes is the console device, and it sets a
global (pci_vga_hose) for later use in managing access to the device. This is
called in "init_arch" on TITAN and TSUNAMI machines; MARVEL machines use a
custom version of this routine because of extra complexity.
A routine, "locate_and_init_vga()", is used to find the graphics device and
set a global (pci_vga_hose) for later use in managing access to the device, in
the case where "find_console_vga_hose" has failed.
Various adjustments are made to the ioremap and ioportmap routines for
detecting and translating "legacy" VGA register and memory references to the
real PCI domain.
[akpm@linux-foundation.org: don't statically init bss]
[akpm@linux-foundation.org: build fix]
Signed-off-by: Jay Estabrook <jay.estabrook@hp.com>
Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-06-01 14:47:03 +07:00
|
|
|
locate_and_init_vga(NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
clipper_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
common_init_pci();
|
|
|
|
|
locate_and_init_vga(NULL);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
webbrick_init_arch(void)
|
|
|
|
|
{
|
|
|
|
|
tsunami_init_arch();
|
|
|
|
|
|
|
|
|
|
/* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
|
|
|
|
|
hose_head->sg_isa->align_entry = 4;
|
|
|
|
|
hose_head->sg_pci->align_entry = 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The System Vectors
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector dp264_mv __initmv = {
|
|
|
|
|
.vector_name = "DP264",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TSUNAMI_IO,
|
|
|
|
|
.machine_check = tsunami_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 64,
|
|
|
|
|
.device_interrupt = dp264_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = tsunami_init_arch,
|
|
|
|
|
.init_irq = dp264_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = dp264_init_pci,
|
|
|
|
|
.kill_arch = tsunami_kill_arch,
|
|
|
|
|
.pci_map_irq = dp264_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(dp264)
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector monet_mv __initmv = {
|
|
|
|
|
.vector_name = "Monet",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TSUNAMI_IO,
|
|
|
|
|
.machine_check = tsunami_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 64,
|
|
|
|
|
.device_interrupt = dp264_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = tsunami_init_arch,
|
|
|
|
|
.init_irq = dp264_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = monet_init_pci,
|
|
|
|
|
.kill_arch = tsunami_kill_arch,
|
|
|
|
|
.pci_map_irq = monet_map_irq,
|
|
|
|
|
.pci_swizzle = monet_swizzle,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector webbrick_mv __initmv = {
|
|
|
|
|
.vector_name = "Webbrick",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TSUNAMI_IO,
|
|
|
|
|
.machine_check = tsunami_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 64,
|
|
|
|
|
.device_interrupt = dp264_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = webbrick_init_arch,
|
|
|
|
|
.init_irq = dp264_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = common_init_pci,
|
|
|
|
|
.kill_arch = tsunami_kill_arch,
|
|
|
|
|
.pci_map_irq = webbrick_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector clipper_mv __initmv = {
|
|
|
|
|
.vector_name = "Clipper",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TSUNAMI_IO,
|
|
|
|
|
.machine_check = tsunami_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 64,
|
|
|
|
|
.device_interrupt = dp264_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = tsunami_init_arch,
|
|
|
|
|
.init_irq = clipper_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
ALPHA: support graphics on non-zero PCI domains
This code replaces earlier and incomplete handling of graphics on non-zero PCI
domains (aka hoses or peer PCI buses).
An option (CONFIG_VGA_HOSE) is set TRUE if configuring a GENERIC kernel, or a
kernel for MARVEL, TITAN, or TSUNAMI machines, as these are the machines whose
SRM consoles are capable of configuring and handling graphics options on
non-zero hoses. All other machines have the option set FALSE.
A routine, "find_console_vga_hose()", is used to find the graphics device
which the machine's firmware believes is the console device, and it sets a
global (pci_vga_hose) for later use in managing access to the device. This is
called in "init_arch" on TITAN and TSUNAMI machines; MARVEL machines use a
custom version of this routine because of extra complexity.
A routine, "locate_and_init_vga()", is used to find the graphics device and
set a global (pci_vga_hose) for later use in managing access to the device, in
the case where "find_console_vga_hose" has failed.
Various adjustments are made to the ioremap and ioportmap routines for
detecting and translating "legacy" VGA register and memory references to the
real PCI domain.
[akpm@linux-foundation.org: don't statically init bss]
[akpm@linux-foundation.org: build fix]
Signed-off-by: Jay Estabrook <jay.estabrook@hp.com>
Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-06-01 14:47:03 +07:00
|
|
|
.init_pci = clipper_init_pci,
|
2005-04-17 05:20:36 +07:00
|
|
|
.kill_arch = tsunami_kill_arch,
|
|
|
|
|
.pci_map_irq = clipper_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Sharks strongly resemble Clipper, at least as far
|
|
|
|
|
* as interrupt routing, etc, so we're using the
|
|
|
|
|
* same functions as Clipper does
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct alpha_machine_vector shark_mv __initmv = {
|
|
|
|
|
.vector_name = "Shark",
|
|
|
|
|
DO_EV6_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_TSUNAMI_IO,
|
|
|
|
|
.machine_check = tsunami_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = TSUNAMI_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = 64,
|
|
|
|
|
.device_interrupt = dp264_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.init_arch = tsunami_init_arch,
|
|
|
|
|
.init_irq = clipper_init_irq,
|
|
|
|
|
.init_rtc = common_init_rtc,
|
|
|
|
|
.init_pci = common_init_pci,
|
|
|
|
|
.kill_arch = tsunami_kill_arch,
|
|
|
|
|
.pci_map_irq = clipper_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* No alpha_mv alias for webbrick/monet/clipper, since we compile them
|
|
|
|
|
in unconditionally with DP264; setup_arch knows how to cope. */
|