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linux_dsm_epyc7002/drivers/soc/qcom/Kconfig

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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 19:07:45 +07:00
# SPDX-License-Identifier: GPL-2.0-only
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-24 23:31:21 +07:00
#
# QCOM Soc drivers
#
soc: qcom: bring all qcom drivers into a submenu As the number of qcom drivers increase, entries in SOC menu looks scattered with other SOC drivers. Make a submenu for Qcom drivers to make it visibly clear while selecting qcom SOC specific drivers. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-07-26 22:27:16 +07:00
menu "Qualcomm SoC drivers"
soc: qcom: Add AOSS QMP driver The Always On Subsystem (AOSS) Qualcomm Messaging Protocol (QMP) driver is used to communicate with the AOSS for certain side-channel requests, that are not available through the RPMh interface. The communication is a very simple synchronous mechanism of messages being written in message RAM and a doorbell in the AOSS is rung. As the AOSS has processed the message length is cleared and an interrupt is fired by the AOSS as acknowledgment. The driver exposes the QDSS clock as a clock and the low-power state associated with the remoteprocs in the system as a set of power-domains. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-12 11:45:34 +07:00
config QCOM_AOSS_QMP
tristate "Qualcomm AOSS Driver"
depends on ARCH_QCOM || COMPILE_TEST
depends on MAILBOX
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors Fix Kconfig warning and subsequent build errors that are caused when PM_GENERIC_DOMAINS=y but CONFIG_PM is not set/enabled. WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS Depends on [n]: PM [=n] Selected by [m]: - QCOM_AOSS_QMP [=m] && (ARCH_QCOM || COMPILE_TEST [=y]) && MAILBOX [=y] && COMMON_CLK [=y] Fixes these build errors: ../drivers/base/power/domain.c: In function ‘genpd_queue_power_off_work’: ../drivers/base/power/domain.c:485:13: error: ‘pm_wq’ undeclared (first use in this function) queue_work(pm_wq, &genpd->power_off_work); ../drivers/base/power/domain.c:485:13: note: each undeclared identifier is reported only once for each function it appears in ../drivers/base/power/domain.c: In function ‘genpd_dev_pm_qos_notifier’: ../drivers/base/power/domain.c:675:25: error: ‘struct dev_pm_info’ has no member named ‘ignore_children’ if (!dev || dev->power.ignore_children) ../drivers/base/power/domain.c: In function ‘rtpm_status_str’: ../drivers/base/power/domain.c:2754:16: error: ‘struct dev_pm_info’ has no member named ‘runtime_error’ if (dev->power.runtime_error) ../drivers/base/power/domain.c:2756:21: error: ‘struct dev_pm_info’ has no member named ‘disable_depth’ else if (dev->power.disable_depth) ../drivers/base/power/domain.c:2758:21: error: ‘struct dev_pm_info’ has no member named ‘runtime_status’ else if (dev->power.runtime_status < ARRAY_SIZE(status_lookup)) ../drivers/base/power/domain.c:2759:31: error: ‘struct dev_pm_info’ has no member named ‘runtime_status’ p = status_lookup[dev->power.runtime_status]; ../drivers/base/power/domain_governor.c: In function ‘default_suspend_ok’: ../drivers/base/power/domain_governor.c:82:17: error: ‘struct dev_pm_info’ has no member named ‘ignore_children’ Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-15 04:47:48 +07:00
depends on COMMON_CLK && PM
soc: qcom: Add AOSS QMP driver The Always On Subsystem (AOSS) Qualcomm Messaging Protocol (QMP) driver is used to communicate with the AOSS for certain side-channel requests, that are not available through the RPMh interface. The communication is a very simple synchronous mechanism of messages being written in message RAM and a doorbell in the AOSS is rung. As the AOSS has processed the message length is cleared and an interrupt is fired by the AOSS as acknowledgment. The driver exposes the QDSS clock as a clock and the low-power state associated with the remoteprocs in the system as a set of power-domains. Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-12 11:45:34 +07:00
select PM_GENERIC_DOMAINS
help
This driver provides the means of communicating with and controlling
the low-power state for resources related to the remoteproc
subsystems as well as controlling the debug clocks exposed by the Always On
Subsystem (AOSS) using Qualcomm Messaging Protocol (QMP).
drivers: qcom: add command DB driver Command DB is a simple database in the shared memory of QCOM SoCs, that provides information regarding shared resources. Some shared resources in the SoC have properties that are probed dynamically at boot by the remote processor. The information pertaining to the SoC and the platform are made available in the shared memory. Drivers can query this information using predefined strings. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-11 00:57:23 +07:00
config QCOM_COMMAND_DB
bool "Qualcomm Command DB"
qcom: cmd-db: enforce CONFIG_OF_RESERVED_MEM dependency Without CONFIG_OF_RESERVED_MEM, gcc sees that the global cmd_db_header variable is never initialized, and through code optimization concludes that a lot of other code cannot possibly work after that: drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_addr': drivers/soc/qcom/cmd-db.c:197:21: error: 'ent.addr' may be used uninitialized in this function [-Werror=maybe-uninitialized] return ret < 0 ? 0 : le32_to_cpu(ent.addr); drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_aux_data': drivers/soc/qcom/cmd-db.c:224:10: error: 'ent.len' may be used uninitialized in this function [-Werror=maybe-uninitialized] ent_len = le16_to_cpu(ent.len); drivers/soc/qcom/cmd-db.c:115:6: error: 'rsc_hdr.data_offset' may be used uninitialized in this function [-Werror=maybe-uninitialized] u16 offset = le16_to_cpu(hdr->data_offset); ^~~~~~ drivers/soc/qcom/cmd-db.c:116:6: error: 'ent.offset' may be used uninitialized in this function [-Werror=maybe-uninitialized] u16 loffset = le16_to_cpu(ent->offset); ^~~~~~~ drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_aux_data_len': drivers/soc/qcom/cmd-db.c:250:38: error: 'ent.len' may be used uninitialized in this function [-Werror=maybe-uninitialized] return ret < 0 ? 0 : le16_to_cpu(ent.len); ^ drivers/soc/qcom/cmd-db.c: In function 'cmd_db_read_slave_id': drivers/soc/qcom/cmd-db.c:272:7: error: 'ent.addr' may be used uninitialized in this function [-Werror=maybe-uninitialized] Using a hard CONFIG_OF_RESERVED_MEM dependency avoids this warning, and we can remove the CONFIG_OF dependency. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-25 23:08:24 +07:00
depends on ARCH_QCOM || COMPILE_TEST
depends on OF_RESERVED_MEM
drivers: qcom: add command DB driver Command DB is a simple database in the shared memory of QCOM SoCs, that provides information regarding shared resources. Some shared resources in the SoC have properties that are probed dynamically at boot by the remote processor. The information pertaining to the SoC and the platform are made available in the shared memory. Drivers can query this information using predefined strings. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-04-11 00:57:23 +07:00
help
Command DB queries shared memory by key string for shared system
resources. Platform drivers that require to set state of a shared
resource on a RPM-hardened platform must use this database to get
SoC specific identifier and information for the shared resources.
PM: AVS: qcom-cpr: Move the driver to the qcom specific drivers The avs drivers are all SoC specific drivers that doesn't share any code. Instead they are located in a directory, mostly to keep similar functionality together. From a maintenance point of view, it makes better sense to collect SoC specific drivers like these, into the SoC specific directories. Therefore, let's move the qcom-cpr driver to the qcom directory. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Niklas Cassel <nks@flawful.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-10-06 23:05:13 +07:00
config QCOM_CPR
tristate "QCOM Core Power Reduction (CPR) support"
depends on ARCH_QCOM && HAS_IOMEM
select PM_OPP
select REGMAP
help
Say Y here to enable support for the CPR hardware found on Qualcomm
SoCs like QCS404.
This driver populates CPU OPPs tables and makes adjustments to the
tables based on feedback from the CPR hardware. If you want to do
CPUfrequency scaling say Y here.
To compile this driver as a module, choose M here: the module will
be called qcom-cpr
soc: qcom: Add GENI based QUP Wrapper driver This driver manages the Generic Interface (GENI) firmware based Qualcomm Universal Peripheral (QUP) Wrapper. GENI based QUP is the next generation programmable module composed of multiple Serial Engines (SE) and supports a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. This driver also enables managing the serial interface independent aspects of Serial Engines. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Signed-off-by: Sagar Dharia <sdharia@codeaurora.org> Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-03-31 00:08:17 +07:00
config QCOM_GENI_SE
tristate "QCOM GENI Serial Engine Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This driver is used to manage Generic Interface (GENI) firmware based
Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper. This
driver is also used to manage the common aspects of multiple Serial
Engines present in the QUP.
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-24 23:31:21 +07:00
config QCOM_GSBI
soc: qcom: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20191120133925.13712-1-krzk@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-11-20 20:39:25 +07:00
tristate "QCOM General Serial Bus Interface"
depends on ARCH_QCOM || COMPILE_TEST
select MFD_SYSCON
help
Say y here to enable GSBI support. The GSBI provides control
functions for connecting the underlying serial UART, SPI, and I2C
devices to the output pins.
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-24 23:31:21 +07:00
drivers: soc: Add LLCC driver LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-24 07:35:21 +07:00
config QCOM_LLCC
tristate "Qualcomm Technologies, Inc. LLCC driver"
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on ARCH_QCOM || COMPILE_TEST
drivers: soc: Add LLCC driver LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-24 07:35:21 +07:00
help
Qualcomm Technologies, Inc. platform specific
soc: qcom: llcc cleanup to get rid of sdm845 specific driver file A single file should suffice the need to program the llcc for various platforms. Get rid of sdm845 specific driver file to make way for a more generic driver. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-07-18 20:02:36 +07:00
Last Level Cache Controller(LLCC) driver for platforms such as,
SDM845. This provides interfaces to clients that use the LLCC.
Say yes here to enable LLCC slice driver.
drivers: soc: Add LLCC driver LLCC (Last Level Cache Controller) provides additional cache memory in the system. LLCC is partitioned into multiple slices and each slice gets its own priority, size, ID and other config parameters. LLCC driver programs these parameters for each slice. Clients that are assigned to use LLCC need to get information such size & ID of the slice they get and activate or deactivate the slice as needed. LLCC driver provides API for the clients to perform these operations. Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org> Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-24 07:35:21 +07:00
soc: qcom: Separate kryo l2 accessors from PMU driver The driver provides kernel level API for other drivers to access the MSM8996 L2 cache registers. Separating the L2 access code from the PMU driver and making it public to allow other drivers use it. The accesses must be separated with a single spinlock, maintained in this driver. Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/1593766185-16346-2-git-send-email-loic.poulain@linaro.org Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-03 15:49:41 +07:00
config QCOM_KRYO_L2_ACCESSORS
bool
depends on ARCH_QCOM && ARM64 || COMPILE_TEST
remoteproc: Move qcom_mdt_loader into drivers/soc/qcom With the remoteproc parts cleaned out of the MDT loader we can move it to drivers/soc/qcom. Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2017-01-27 18:12:57 +07:00
config QCOM_MDT_LOADER
tristate
select QCOM_SCM
soc: qcom: add OCMEM driver The OCMEM driver handles allocation and configuration of the On Chip MEMory that is present on some Snapdragon SoCs. Devices which have OCMEM do not have GMEM inside the GPU core, so the GPU must instead use OCMEM to be functional. Since the GPU is currently the only OCMEM user with an upstream driver, this is just a minimal implementation sufficient for statically allocating to the GPU it's chunk of OCMEM. This driver currently does not read the gmu-sram node that is described in the device tree bindings. The starting memory address of the GPU's reserved memory region is hardcoded to zero to match what the hardware expects. The driver can be updated to read the reserved memory regions from device tree once other users of OCMEM are added upstream. Signed-off-by: Brian Masney <masneyb@onstation.org> Co-developed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Gabriel Francisco <frc.gabrielgmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-08-23 19:16:35 +07:00
config QCOM_OCMEM
tristate "Qualcomm On Chip Memory (OCMEM) driver"
depends on ARCH_QCOM
select QCOM_SCM
help
soc: qcom: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20191120133925.13712-1-krzk@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-11-20 20:39:25 +07:00
The On Chip Memory (OCMEM) allocator allows various clients to
allocate memory from OCMEM based on performance, latency and power
requirements. This is typically used by the GPU, camera/video, and
audio components on some Snapdragon SoCs.
soc: qcom: add OCMEM driver The OCMEM driver handles allocation and configuration of the On Chip MEMory that is present on some Snapdragon SoCs. Devices which have OCMEM do not have GMEM inside the GPU core, so the GPU must instead use OCMEM to be functional. Since the GPU is currently the only OCMEM user with an upstream driver, this is just a minimal implementation sufficient for statically allocating to the GPU it's chunk of OCMEM. This driver currently does not read the gmu-sram node that is described in the device tree bindings. The starting memory address of the GPU's reserved memory region is hardcoded to zero to match what the hardware expects. The driver can be updated to read the reserved memory regions from device tree once other users of OCMEM are added upstream. Signed-off-by: Brian Masney <masneyb@onstation.org> Co-developed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Gabriel Francisco <frc.gabrielgmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-08-23 19:16:35 +07:00
soc: qcom: Introduce Protection Domain Restart helpers Qualcomm SoCs (starting with MSM8998) allow for multiple protection domains to run on the same Q6 sub-system. This allows for services like ATH10K WLAN FW to have their own separate address space and crash/recover without disrupting the modem and other PDs running on the same sub-system. The PDR helpers introduces an abstraction that allows for tracking/controlling the life cycle of protection domains running on various Q6 sub-systems. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200312120842.21991-2-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-12 19:08:40 +07:00
config QCOM_PDR_HELPERS
tristate
select QCOM_QMI_HELPERS
soc: qcom: Introduce QMI encoder/decoder Add the helper library for encoding and decoding QMI encoded messages. The implementation is taken from lib/qmi_encdec.c of the Qualcomm kernel (msm-3.18). Modifications has been made to the public API, source buffers has been made const and the debug-logging part was omitted, for now. Acked-by: Chris Lew <clew@codeaurora.org> Tested-by: Chris Lew <clew@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-12-06 00:43:06 +07:00
config QCOM_QMI_HELPERS
tristate
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on NET
soc: qcom: Introduce QMI encoder/decoder Add the helper library for encoding and decoding QMI encoded messages. The implementation is taken from lib/qmi_encdec.c of the Qualcomm kernel (msm-3.18). Modifications has been made to the public API, source buffers has been made const and the debug-logging part was omitted, for now. Acked-by: Chris Lew <clew@codeaurora.org> Tested-by: Chris Lew <clew@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-12-06 00:43:06 +07:00
soc: qcom: Remote filesystem memory driver The Qualcomm remote file system protocol is used by certain remoteprocs, in particular the modem, to read and write persistent storage in platforms where only the application CPU has physical storage access. The protocol is based on a set of QMI-encoded control-messages and a shared memory buffer for exchaning the data. This driver implements the latter, providing the user space service access to the carved out chunk of memory. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-17 01:17:08 +07:00
config QCOM_RMTFS_MEM
tristate "Qualcomm Remote Filesystem memory driver"
depends on ARCH_QCOM
soc: qcom: rmtfs-mem: Add support for assigning memory to remote On some platform the remote processor's memory map is not statically configured in TrustZone, so each memory region that is to be accessed by the remote needs a call into TrustZone to set up the remote's permissions. Implement this for the rmtfs memory driver, to give the modem on 8996 access to the shared file system buffers. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-02-13 08:37:23 +07:00
select QCOM_SCM
soc: qcom: Remote filesystem memory driver The Qualcomm remote file system protocol is used by certain remoteprocs, in particular the modem, to read and write persistent storage in platforms where only the application CPU has physical storage access. The protocol is based on a set of QMI-encoded control-messages and a shared memory buffer for exchaning the data. This driver implements the latter, providing the user space service access to the carved out chunk of memory. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-10-17 01:17:08 +07:00
help
The Qualcomm remote filesystem memory driver is used for allocating
and exposing regions of shared memory with remote processors for the
purpose of exchanging sector-data between the remote filesystem
service and its clients.
Say y here if you intend to boot the modem remoteproc.
drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs Add controller driver for QCOM SoCs that have hardware based shared resource management. The hardware IP known as RSC (Resource State Coordinator) houses multiple Direct Resource Voter (DRV) for different execution levels. A DRV is a unique voter on the state of a shared resource. A Trigger Control Set (TCS) is a bunch of slots that can house multiple resource state requests, that when triggered will issue those requests through an internal bus to the Resource Power Manager Hardened (RPMH) blocks. These hardware blocks are capable of adjusting clocks, voltages, etc. The resource state request from a DRV are aggregated along with state requests from other processors in the SoC and the aggregate value is applied on the resource. Some important aspects of the RPMH communication - - Requests are <addr, value> with some header information - Multiple requests (upto 16) may be sent through a TCS, at a time - Requests in a TCS are sent in sequence - Requests may be fire-n-forget or completion (response expected) - Multiple TCS from the same DRV may be triggered simultaneously - Cannot send a request if another request for the same addr is in progress from the same DRV - When all the requests from a TCS are complete, an IRQ is raised - The IRQ handler needs to clear the TCS before it is available for reuse - TCS configuration is specific to a DRV - Platform drivers may use DRV from different RSCs to make requests Resource state requests made when CPUs are active are called 'active' state requests. Requests made when all the CPUs are powered down (idle state) are called 'sleep' state requests. They are matched by a corresponding 'wake' state requests which puts the resources back in to previously requested active state before resuming any CPU. TCSes are dedicated for each type of requests. Active mode TCSes (AMC) are used to send requests immediately to the resource, while control TCS are used to provide specific information to the controller. Sleep and Wake TCS send sleep and wake requests, after and before the system halt respectively. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-06-20 20:26:58 +07:00
config QCOM_RPMH
bool "Qualcomm RPM-Hardened (RPMH) Communication"
soc: qcom: rpmh: Allow RPMH on ARM SoC Remove config restriction for RPMH on ARM64 platforms only. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Link: https://lore.kernel.org/r/1590750158-20661-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-05-29 18:02:38 +07:00
depends on ARCH_QCOM || COMPILE_TEST
drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs Add controller driver for QCOM SoCs that have hardware based shared resource management. The hardware IP known as RSC (Resource State Coordinator) houses multiple Direct Resource Voter (DRV) for different execution levels. A DRV is a unique voter on the state of a shared resource. A Trigger Control Set (TCS) is a bunch of slots that can house multiple resource state requests, that when triggered will issue those requests through an internal bus to the Resource Power Manager Hardened (RPMH) blocks. These hardware blocks are capable of adjusting clocks, voltages, etc. The resource state request from a DRV are aggregated along with state requests from other processors in the SoC and the aggregate value is applied on the resource. Some important aspects of the RPMH communication - - Requests are <addr, value> with some header information - Multiple requests (upto 16) may be sent through a TCS, at a time - Requests in a TCS are sent in sequence - Requests may be fire-n-forget or completion (response expected) - Multiple TCS from the same DRV may be triggered simultaneously - Cannot send a request if another request for the same addr is in progress from the same DRV - When all the requests from a TCS are complete, an IRQ is raised - The IRQ handler needs to clear the TCS before it is available for reuse - TCS configuration is specific to a DRV - Platform drivers may use DRV from different RSCs to make requests Resource state requests made when CPUs are active are called 'active' state requests. Requests made when all the CPUs are powered down (idle state) are called 'sleep' state requests. They are matched by a corresponding 'wake' state requests which puts the resources back in to previously requested active state before resuming any CPU. TCSes are dedicated for each type of requests. Active mode TCSes (AMC) are used to send requests immediately to the resource, while control TCS are used to provide specific information to the controller. Sleep and Wake TCS send sleep and wake requests, after and before the system halt respectively. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-06-20 20:26:58 +07:00
help
Support for communication with the hardened-RPM blocks in
Qualcomm Technologies Inc (QTI) SoCs. RPMH communication uses an
internal bus to transmit state requests for shared resources. A set
of hardware components aggregate requests for these resources and
help apply the aggregated state on the resource.
soc: qcom: rpmhpd: Add RPMh power domain driver The RPMh power domain driver aggregates the corner votes from various consumers for the ARC resources and communicates it to RPMh. With RPMh we use 2 different numbering space for corners, one used by the clients to express their performance needs, and another used to communicate to RPMh hardware. The clients express their performance requirements using a sparse numbering space which are mapped to meaningful levels like RET, SVS, NOMINAL, TURBO etc which then get mapped to another number space between 0 and 15 which is communicated to RPMh. The sparse number space, also referred to as vlvl is mapped to the continuous number space of 0 to 15, also referred to as hlvl, using command DB. Some power domain clients could request a performance state only while the CPU is active, while some others could request for a certain performance state all the time regardless of the state of the CPU. We handle this by internally aggregating the votes from both type of clients and then send the aggregated votes to RPMh. There are also 3 different types of votes that are comunicated to RPMh for every resource. 1. ACTIVE_ONLY: This specifies the requirement for the resource when the CPU is active 2. SLEEP: This specifies the requirement for the resource when the CPU is going to sleep 3. WAKE_ONLY: This specifies the requirement for the resource when the CPU is coming out of sleep to active state We add data for all power domains on sdm845 SoC as part of the patch. The driver can be extended to support other SoCs which support RPMh Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-10 11:02:07 +07:00
config QCOM_RPMHPD
soc: qcom: rpmhpd: Allow RPMHPD driver to be loaded as a module This patch allow the rpmhpd driver to be loaded as a permenent module. Meaning it can be loaded from a module, but then cannot be unloaded. Ideally, it would include a remove hook and related logic, but apparently the genpd code isn't able to track usage and cleaning things up? So making it a permenent module at least improves things slightly over requiring it to be a built in driver. Cc: Todd Kjos <tkjos@google.com> Cc: Saravana Kannan <saravanak@google.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org Acked-by: Saravana Kannan <saravanak@google.com> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Link: https://lore.kernel.org/r/20200326224459.105170-4-john.stultz@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-27 05:44:59 +07:00
tristate "Qualcomm RPMh Power domain driver"
soc: qcom: rpmhpd: Add RPMh power domain driver The RPMh power domain driver aggregates the corner votes from various consumers for the ARC resources and communicates it to RPMh. With RPMh we use 2 different numbering space for corners, one used by the clients to express their performance needs, and another used to communicate to RPMh hardware. The clients express their performance requirements using a sparse numbering space which are mapped to meaningful levels like RET, SVS, NOMINAL, TURBO etc which then get mapped to another number space between 0 and 15 which is communicated to RPMh. The sparse number space, also referred to as vlvl is mapped to the continuous number space of 0 to 15, also referred to as hlvl, using command DB. Some power domain clients could request a performance state only while the CPU is active, while some others could request for a certain performance state all the time regardless of the state of the CPU. We handle this by internally aggregating the votes from both type of clients and then send the aggregated votes to RPMh. There are also 3 different types of votes that are comunicated to RPMh for every resource. 1. ACTIVE_ONLY: This specifies the requirement for the resource when the CPU is active 2. SLEEP: This specifies the requirement for the resource when the CPU is going to sleep 3. WAKE_ONLY: This specifies the requirement for the resource when the CPU is coming out of sleep to active state We add data for all power domains on sdm845 SoC as part of the patch. The driver can be extended to support other SoCs which support RPMh Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-10 11:02:07 +07:00
depends on QCOM_RPMH && QCOM_COMMAND_DB
help
QCOM RPMh Power domain driver to support power-domains with
performance states. The driver communicates a performance state
value to RPMh which then translates it into corresponding voltage
for the voltage rail.
soc: qcom: rpmpd: Add a Power domain driver to model corners The Power domains for corners just pass the performance state set by the consumers to the RPM (Remote Power manager) which then takes care of setting the appropriate voltage on the corresponding rails to meet the performance needs. We add all power domain data needed on msm8996 here. This driver can easily be extended by adding data for other qualcomm SoCs as well. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-10 11:02:04 +07:00
config QCOM_RPMPD
soc: qcom: rpmpd: Allow RPMPD driver to be loaded as a module This patch allow the rpmpd driver to be loaded as a permenent module. Meaning it can be loaded from a module, but then cannot be unloaded. Ideally, it would include a remove hook and related logic, but apparently the genpd code isn't able to track usage and cleaning things up? (See: https://lkml.org/lkml/2019/1/24/38) So making it a permenent module at least improves things slightly over requiring it to be a built in driver. Cc: Todd Kjos <tkjos@google.com> Cc: Saravana Kannan <saravanak@google.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org Acked-by: Saravana Kannan <saravanak@google.com> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Link: https://lore.kernel.org/r/20200326224459.105170-2-john.stultz@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-27 05:44:57 +07:00
tristate "Qualcomm RPM Power domain driver"
depends on QCOM_SMD_RPM
soc: qcom: rpmpd: Add a Power domain driver to model corners The Power domains for corners just pass the performance state set by the consumers to the RPM (Remote Power manager) which then takes care of setting the appropriate voltage on the corresponding rails to meet the performance needs. We add all power domain data needed on msm8996 here. This driver can easily be extended by adding data for other qualcomm SoCs as well. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-10 11:02:04 +07:00
help
QCOM RPM Power domain driver to support power-domains with
performance states. The driver communicates a performance state
value to RPM which then translates it into corresponding voltage
for the voltage rail.
soc: qcom: Reorder SMEM/SMD configs When I make nconfig, having the SMEM option after the SMD option causes the configurator to get confused when I'm enabling and disabling these options. Let's move SMEM before SMD so there's a clear indented dependency chain. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-08-29 01:23:33 +07:00
config QCOM_SMEM
tristate "Qualcomm Shared Memory Manager (SMEM)"
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on ARCH_QCOM || COMPILE_TEST
soc: qcom/smem: add HWSPINLOCK dependency This fixes a build error when smem is enabled without hwspinlock: drivers/built-in.o: In function `qcom_smem_alloc': rockchip-efuse.c:(.text+0x7a3e4): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7a568): undefined reference to `__hwspin_unlock' drivers/built-in.o: In function `qcom_smem_remove': rockchip-efuse.c:(.text+0x7a5cc): undefined reference to `hwspin_lock_free' drivers/built-in.o: In function `qcom_smem_probe': rockchip-efuse.c:(.text+0x7a960): undefined reference to `hwspin_lock_request_specific' rockchip-efuse.c:(.text+0x7a988): undefined reference to `of_hwspin_lock_get_id' drivers/built-in.o: In function `qcom_smem_get': rockchip-efuse.c:(.text+0x7aa24): undefined reference to `__hwspin_lock_timeout' rockchip-efuse.c:(.text+0x7aafc): undefined reference to `__hwspin_unlock' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-10-13 22:05:39 +07:00
depends on HWSPINLOCK
soc: qcom: Reorder SMEM/SMD configs When I make nconfig, having the SMEM option after the SMD option causes the configurator to get confused when I'm enabling and disabling these options. Let's move SMEM before SMD so there's a clear indented dependency chain. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-08-29 01:23:33 +07:00
help
Say y here to enable support for the Qualcomm Shared Memory Manager.
The driver provides an interface to items in a heap shared among all
processors in a Qualcomm platform.
soc: qcom: Driver for the Qualcomm RPM over SMD Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28 10:20:32 +07:00
config QCOM_SMD_RPM
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on ARCH_QCOM || COMPILE_TEST
soc: qcom: Remove bogus depends on OF from QCOM_SMD_RPM QCOM_SMD_RPM builds perfectly fine without CONFIG_OF set. Remove the bogus depends on OF. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:19 +07:00
depends on RPMSG
soc: qcom: Driver for the Qualcomm RPM over SMD Driver for the Resource Power Manager (RPM) found in Qualcomm 8974 based devices. The driver exposes resources that child drivers can operate on; to implementing regulator, clock and bus frequency drivers. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28 10:20:32 +07:00
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8974 based
devices.
This is required to access many regulators, clocks and bus
frequencies controlled by the RPM on these devices.
Say M here if you want to include support for the Qualcomm RPM as a
module. This will build a module called "qcom-smd-rpm".
soc: qcom: Introduce common SMEM state machine code This implements a common API for handling and exposing SMP2P and SMSM state information. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:01 +07:00
config QCOM_SMEM_STATE
bool
soc: qcom: smsm: Add driver for Qualcomm SMSM This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:02 +07:00
soc: qcom: smp2p: Qualcomm Shared Memory Point to Point Introduce the Qualcomm Shard Memory Point to Point driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:03 +07:00
config QCOM_SMP2P
soc: qcom: enable smsm/smp2p modular build The newly added smp2p and smsm drivers cannot be loadable modules but depend on smem, which can be, and that causes a link error: drivers/built-in.o: In function `qcom_smp2p_intr': :(.text+0xa6e68): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smp2p_probe': :(.text+0xa7320): undefined reference to `qcom_smem_alloc' :(.text+0xa736c): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smsm_probe': :(.text+0xa7b34): undefined reference to `qcom_smem_get' This marks all the drivers as 'tristate' to make the Kconfig dependency resolution work properly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: dbb04bd7122f ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point") Fixes: d7387fc6add4 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-11-20 17:32:21 +07:00
tristate "Qualcomm Shared Memory Point to Point support"
soc: qcom: smp2p: Access APCS as mailbox client Attempt to acquire the APCS IPC through the mailbox framework and fall back to the old syscon based approach, to allow us to move away from using the syscon. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-11-30 07:00:40 +07:00
depends on MAILBOX
soc: qcom: smp2p: Qualcomm Shared Memory Point to Point Introduce the Qualcomm Shard Memory Point to Point driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:03 +07:00
depends on QCOM_SMEM
select QCOM_SMEM_STATE
soc: qcom: smp2p: Add select IRQ_DOMAIN Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smp2p.c: In function ‘qcom_smp2p_inbound_entry’: drivers/soc/qcom/smp2p.c:317:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, &smp2p_irq_ops, entry); ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:17 +07:00
select IRQ_DOMAIN
soc: qcom: smp2p: Qualcomm Shared Memory Point to Point Introduce the Qualcomm Shard Memory Point to Point driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:03 +07:00
help
Say yes here to support the Qualcomm Shared Memory Point to Point
protocol.
soc: qcom: smsm: Add driver for Qualcomm SMSM This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:02 +07:00
config QCOM_SMSM
soc: qcom: enable smsm/smp2p modular build The newly added smp2p and smsm drivers cannot be loadable modules but depend on smem, which can be, and that causes a link error: drivers/built-in.o: In function `qcom_smp2p_intr': :(.text+0xa6e68): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smp2p_probe': :(.text+0xa7320): undefined reference to `qcom_smem_alloc' :(.text+0xa736c): undefined reference to `qcom_smem_get' drivers/built-in.o: In function `qcom_smsm_probe': :(.text+0xa7b34): undefined reference to `qcom_smem_get' This marks all the drivers as 'tristate' to make the Kconfig dependency resolution work properly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: dbb04bd7122f ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point") Fixes: d7387fc6add4 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-11-20 17:32:21 +07:00
tristate "Qualcomm Shared Memory State Machine"
soc: qcom: smsm: Add driver for Qualcomm SMSM This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:02 +07:00
depends on QCOM_SMEM
select QCOM_SMEM_STATE
soc: qcom: smsm: Add select IRQ_DOMAIN Since we are using irq_domain_add_linear(), add a select on IRQ_DOMAIN. This is needed in order to be able to remove the depends on ARCH_QCOM. drivers/soc/qcom/smsm.c: In function ‘smsm_inbound_entry’: drivers/soc/qcom/smsm.c:411:18: error: implicit declaration of function ‘irq_domain_add_linear’ entry->domain = irq_domain_add_linear(node, 32, &smsm_irq_ops, entry); ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:18 +07:00
select IRQ_DOMAIN
soc: qcom: smsm: Add driver for Qualcomm SMSM This driver exposed the Qualcomm Shared Memory State Machine bits. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-25 08:25:02 +07:00
help
Say yes here to support the Qualcomm Shared Memory State Machine.
The state machine is represented by bits in shared memory.
soc: qcom: Introduce WCNSS_CTRL SMD client The WCNSS_CTRL SMD client is used for among other things upload nv firmware to a newly booted WCNSS chip. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-22 00:52:55 +07:00
soc: qcom: Add socinfo driver The Qualcomm socinfo driver exposes information about the SoC, its version and its serial number to user space. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Imran Khan <kimran@codeaurora.org> [Bjorn: Extract code to platform_driver, split patch in multiple] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [Vaishali: Simplify declarations, introduce qcom_socinfo struct, Fix memory leak, Remove extra code and Misc code refactoring] Signed-off-by: Vaishali Thakkar <vaishali.thakkar@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-07-24 05:35:13 +07:00
config QCOM_SOCINFO
tristate "Qualcomm socinfo driver"
depends on QCOM_SMEM
select SOC_BUS
help
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.
soc: qcom: Introduce WCNSS_CTRL SMD client The WCNSS_CTRL SMD client is used for among other things upload nv firmware to a newly booted WCNSS chip. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-22 00:52:55 +07:00
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on ARCH_QCOM || COMPILE_TEST
soc: qcom: smd: Transition client drivers from smd to rpmsg By moving these client drivers to use RPMSG instead of the direct SMD API we can reuse them ontop of the newly added GLINK wire-protocol support found in the 820 and 835 Qualcomm platforms. As the new (RPMSG-based) and old SMD implementations are mutually exclusive we have to change all client drivers in one commit, to make sure we have a working system before and after this transition. Acked-by: Andy Gross <andy.gross@linaro.org> Acked-by: Kalle Valo <kvalo@codeaurora.org> Acked-by: Marcel Holtmann <marcel@holtmann.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-28 12:26:33 +07:00
depends on RPMSG
soc: qcom: Introduce WCNSS_CTRL SMD client The WCNSS_CTRL SMD client is used for among other things upload nv firmware to a newly booted WCNSS chip. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-09-22 00:52:55 +07:00
help
Client driver for the WCNSS_CTRL SMD channel, used to download nv
firmware to a newly booted WCNSS chip.
soc: qcom: bring all qcom drivers into a submenu As the number of qcom drivers increase, entries in SOC menu looks scattered with other SOC drivers. Make a submenu for Qcom drivers to make it visibly clear while selecting qcom SOC specific drivers. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-07-26 22:27:16 +07:00
soc: qcom: Add APR bus driver This patch adds support to APR bus (Asynchronous Packet Router) driver. APR driver is made as a bus driver so that the apr devices can added removed more dynamically depending on the state of the services on the dsp. APR is used for communication between application processor and QDSP to use services on QDSP like Audio and others. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-09 19:56:13 +07:00
config QCOM_APR
tristate "Qualcomm APR Bus (Asynchronous Packet Router)"
soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs Since commit cab673583d96 ("soc: Unconditionally include qcom Makefile"), we unconditionally include the soc/qcom/Makefile. This opens up the possibility to compile test the code even when building for other architectures. Allow COMPILE_TEST for all qcom SoC Kconfigs, except for two Kconfigs that depend on QCOM_SCM, since that triggers lots of build errors in qcom_scm. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-08-29 14:57:23 +07:00
depends on ARCH_QCOM || COMPILE_TEST
soc: qcom: Add APR bus driver This patch adds support to APR bus (Asynchronous Packet Router) driver. APR driver is made as a bus driver so that the apr devices can added removed more dynamically depending on the state of the services on the dsp. APR is used for communication between application processor and QDSP to use services on QDSP like Audio and others. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-09 19:56:13 +07:00
depends on RPMSG
soc: qcom: Fix QCOM_APR dependencies QCOM_APR selects QCOM_PDR_HELPERS, which in turn selects QCOM_QMI_HELPERS, which depends on NET. So ensure that APR's dependencies are met by making it depend on NET as well. Fixes: 834735662602 ("soc: qcom: apr: Add avs/audio tracking functionality") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-17 05:03:53 +07:00
depends on NET
soc: qcom: apr: Add avs/audio tracking functionality Use PDR helper functions to track the protection domains that the apr services are dependent upon on SDM845 SoC, specifically the "avs/audio" service running on ADSP Q6. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200312120842.21991-4-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-12 19:08:42 +07:00
select QCOM_PDR_HELPERS
soc: qcom: Add APR bus driver This patch adds support to APR bus (Asynchronous Packet Router) driver. APR driver is made as a bus driver so that the apr devices can added removed more dynamically depending on the state of the services on the dsp. APR is used for communication between application processor and QDSP to use services on QDSP like Audio and others. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-and-tested-by: Rohit kumar <rohitkr@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-09 19:56:13 +07:00
help
soc: qcom: Fix Kconfig indentation Adjust indentation from spaces to tab (+optional two spaces) as in coding style with command like: $ sed -e 's/^ /\t/' -i */Kconfig Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20191120133925.13712-1-krzk@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-11-20 20:39:25 +07:00
Enable APR IPC protocol support between
application processor and QDSP6. APR is
used by audio driver to configure QDSP6
ASM, ADM and AFE modules.
soc: qcom: bring all qcom drivers into a submenu As the number of qcom drivers increase, entries in SOC menu looks scattered with other SOC drivers. Make a submenu for Qcom drivers to make it visibly clear while selecting qcom SOC specific drivers. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-07-26 22:27:16 +07:00
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