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linux_dsm_epyc7002/drivers/net/dsa/mv88e6xxx/global1.h

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net: dsa: mv88e6xxx: add global1 helpers The Global (1) internal SMI device is an extended set of registers containing ATU, PPU, VTU, STU, etc. It is present on every switches, usually at SMI address 0x1B. But old models such as 88E6060 access it at address 0xF, thus using REG_GLOBAL is erroneous. Add a global1_addr info member used by mv88e6xxx_g1_{read,write} and mv88e6xxx_g1_wait helpers in a new global1.c file. This patch finally removes _mv88e6xxx_reg_{read,write}, in favor on the appropriate helpers. No functional changes here. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-09-29 23:21:53 +07:00
/*
* Marvell 88E6xxx Switch Global (1) Registers support
*
* Copyright (c) 2008 Marvell Semiconductor
*
* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef _MV88E6XXX_GLOBAL1_H
#define _MV88E6XXX_GLOBAL1_H
#include "mv88e6xxx.h"
int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
net: dsa: mv88e6xxx: add a soft reset operation Marvell chips have different way to issue a software reset. Old chips (such as 88E6060) have a reset bit in an ATU control register. Newer chips moved this bit in a Global control register. Chips with controllable PPU should reset the PPU when resetting the switch. Add a new reset operation to implement these differences and introduce a mv88e6xxx_software_reset() helper to wrap it conveniently. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-12-06 05:30:27 +07:00
int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
net: dsa: mv88e6xxx: add PPU operations Some Marvell chips can enable/disable the PPU on demand. This is needed to access the PHY registers when there is no indirection mechanism. Add two new ppu_enable and ppu_disable ops to describe this and finally get rid of the MV88E6XXX_FLAG_PPU* flags. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-12-06 05:30:28 +07:00
int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
net: dsa: mv88e6xxx: Move g1 stats code in global1.[ch] Move the stats functions which access global 1 registers into global1.c. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-22 05:27:05 +07:00
int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
net: dsa: mv88e6xxx: Abstract stats_snapshot into ops structure Taking a stats snapshot differs between same families. Abstract this into an ops member. At the same time, move the code into global1.[ch], since the registers are in the global1 range. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-22 05:26:58 +07:00
int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
net: dsa: mv88e6xxx: Add mv88e6390 stats snapshot operation The MV88E6390 has a control register for what the histogram statistics actually contain. This means the stat_snapshot method should not set this information. So implement the 6390 stats_snapshot function without these bits. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-22 05:27:00 +07:00
int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
net: dsa: mv88e6xxx: Add mv88e6390 statistics unit init The statistics unit on the mv88e6390 needs the histogram mode to be configured in a different register compared to other devices. Add an ops to do this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> v2: Rename to mv88e6390_g1_stats_set_histogram Move into global1.c Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-22 05:27:01 +07:00
int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
net: dsa: mv88e6xxx: Move g1 stats code in global1.[ch] Move the stats functions which access global 1 registers into global1.c. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-22 05:27:05 +07:00
void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
net: dsa: mv88e6xxx: Monitor and Management tables The mv88e6390 changes the monitor control register into the Monitor and Management control, which is an indirection register to various registers. Add ops to set the CPU port and the ingress/egress port for both register layouts, to global1 Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-12-03 10:35:17 +07:00
int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
net: dsa: mv88e6xxx: Reserved Management frames to CPU Older devices have a couple of registers in global2. The mv88e6390 family has a single register in global1 behind which hides similar configuration. Implement and op for this. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-12-03 10:45:16 +07:00
int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
net: dsa: mv88e6xxx: add global1 helpers The Global (1) internal SMI device is an extended set of registers containing ATU, PPU, VTU, STU, etc. It is present on every switches, usually at SMI address 0x1B. But old models such as 88E6060 access it at address 0xF, thus using REG_GLOBAL is erroneous. Add a global1_addr info member used by mv88e6xxx_g1_{read,write} and mv88e6xxx_g1_wait helpers in a new global1.c file. This patch finally removes _mv88e6xxx_reg_{read,write}, in favor on the appropriate helpers. No functional changes here. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-09-29 23:21:53 +07:00
net: dsa: mv88e6xxx: enable ATU Learn2All The ATU Learn2All feature allows newly learnt addresses to be spanned on ports marked as "Message Port", currently all DSA ports. This commit enables this feature which is necessary and quite convenient for multi-chip switch fabrics. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:51 +07:00
int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
net: dsa: mv88e6xxx: move ATU ageing time setter Move the ATU ageing time setter code in a new global1_atu.c file, which will be extended in future patches to contains all consequent Global (1) ATU support code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:48 +07:00
int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
unsigned int msecs);
net: dsa: mv88e6xxx: rework ATU GetNext Add and use a fresh documented implementation of the ATU GetNext. Since it is not necessary to write the MAC address to iterate from, only do it once directly in the ATU GetNext operation, if the provided ATU entry structure is not valid. This makes the user code simpler. Also, there is no need to loop when getting a single ATU entry. So remove the mv88e6xxx_atu_get helper and add a simpler snippet in mv88e6xxx_port_db_load_purge to lookup a given MAC address. The _mv88e6xxx_atu_mac_{read,write} are not used anymore thus remove them. _mv88e6xxx_atu_data_{read,write} are still used so keep them. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:53 +07:00
int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
struct mv88e6xxx_atu_entry *entry);
net: dsa: mv88e6xxx: rework ATU Load/Purge All Marvell switch chips have an ATU accessed using the same Global (1) register layout. Only the handling of the FID differs as more bits were necessary to support more and more databases. Add and use a fresh documented implementation of the ATU Load/Purge. The static mv88e6xxx_g1_atu_{fid_write,op_wait,op,data_write,mac_write} functions won't need to be exposed in the end so for the moment keep their counterparts _mv88e6xxx_atu_{wait,cmd,data_write,mac_write} as is, since they are still used by other ATU operations. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:52 +07:00
int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
struct mv88e6xxx_atu_entry *entry);
net: dsa: mv88e6xxx: rework ATU Flush Add a fresh documented implementation of the ATU Flush/Move operation. Use it to replace the current ATU Flush operation. _mv88e6xxx_atu_flush_move is still used by the Move operation so keep it until the Move operation is refactored in a next commit. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:54 +07:00
int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
net: dsa: mv88e6xxx: move ATU ageing time setter Move the ATU ageing time setter code in a new global1_atu.c file, which will be extended in future patches to contains all consequent Global (1) ATU support code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-12 04:12:48 +07:00
net: dsa: mv88e6xxx: add global1 helpers The Global (1) internal SMI device is an extended set of registers containing ATU, PPU, VTU, STU, etc. It is present on every switches, usually at SMI address 0x1B. But old models such as 88E6060 access it at address 0xF, thus using REG_GLOBAL is erroneous. Add a global1_addr info member used by mv88e6xxx_g1_{read,write} and mv88e6xxx_g1_wait helpers in a new global1.c file. This patch finally removes _mv88e6xxx_reg_{read,write}, in favor on the appropriate helpers. No functional changes here. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-09-29 23:21:53 +07:00
#endif /* _MV88E6XXX_GLOBAL1_H */
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