License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2015-03-30 22:32:52 +07:00
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/*
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* Support for Vector Instructions
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*
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* Assembler macros to generate .byte/.word code for particular
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* vector instructions that are supported by recent binutils (>= 2.26) only.
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*
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* Copyright IBM Corp. 2015
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*/
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#ifndef __ASM_S390_VX_INSN_H
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#define __ASM_S390_VX_INSN_H
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#ifdef __ASSEMBLY__
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/* Macros to generate vector instruction byte code */
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/* GR_NUM - Retrieve general-purpose register number
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*
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* @opd: Operand to store register number
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* @r64: String designation register in the format "%rN"
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*/
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.macro GR_NUM opd gr
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2016-08-25 15:40:19 +07:00
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\opd = 255
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2015-03-30 22:32:52 +07:00
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.ifc \gr,%r0
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\opd = 0
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.endif
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.ifc \gr,%r1
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\opd = 1
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.endif
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.ifc \gr,%r2
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\opd = 2
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.endif
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.ifc \gr,%r3
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\opd = 3
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.endif
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.ifc \gr,%r4
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\opd = 4
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.endif
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.ifc \gr,%r5
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\opd = 5
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.endif
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.ifc \gr,%r6
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\opd = 6
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.endif
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.ifc \gr,%r7
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\opd = 7
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.endif
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.ifc \gr,%r8
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\opd = 8
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.endif
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.ifc \gr,%r9
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\opd = 9
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.endif
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.ifc \gr,%r10
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\opd = 10
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.endif
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.ifc \gr,%r11
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\opd = 11
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.endif
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.ifc \gr,%r12
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\opd = 12
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.endif
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.ifc \gr,%r13
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\opd = 13
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.endif
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.ifc \gr,%r14
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\opd = 14
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.endif
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.ifc \gr,%r15
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\opd = 15
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.endif
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2016-08-25 15:40:19 +07:00
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.if \opd == 255
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\opd = \gr
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2015-03-30 22:32:52 +07:00
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.endif
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.endm
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/* VX_NUM - Retrieve vector register number
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*
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* @opd: Operand to store register number
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* @vxr: String designation register in the format "%vN"
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*
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* The vector register number is used for as input number to the
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* instruction and, as well as, to compute the RXB field of the
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2016-08-25 15:40:19 +07:00
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* instruction.
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2015-03-30 22:32:52 +07:00
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*/
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.macro VX_NUM opd vxr
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2016-08-25 15:40:19 +07:00
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\opd = 255
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2015-03-30 22:32:52 +07:00
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.ifc \vxr,%v0
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\opd = 0
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.endif
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.ifc \vxr,%v1
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\opd = 1
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.endif
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.ifc \vxr,%v2
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\opd = 2
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.endif
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.ifc \vxr,%v3
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\opd = 3
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.endif
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.ifc \vxr,%v4
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\opd = 4
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.endif
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.ifc \vxr,%v5
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\opd = 5
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.endif
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.ifc \vxr,%v6
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\opd = 6
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.endif
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.ifc \vxr,%v7
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\opd = 7
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.endif
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.ifc \vxr,%v8
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\opd = 8
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.endif
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.ifc \vxr,%v9
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\opd = 9
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.endif
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.ifc \vxr,%v10
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\opd = 10
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.endif
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.ifc \vxr,%v11
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\opd = 11
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.endif
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.ifc \vxr,%v12
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\opd = 12
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.endif
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.ifc \vxr,%v13
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\opd = 13
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.endif
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.ifc \vxr,%v14
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\opd = 14
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.endif
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.ifc \vxr,%v15
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\opd = 15
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.endif
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.ifc \vxr,%v16
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\opd = 16
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.endif
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.ifc \vxr,%v17
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\opd = 17
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.endif
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.ifc \vxr,%v18
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\opd = 18
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.endif
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.ifc \vxr,%v19
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\opd = 19
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.endif
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.ifc \vxr,%v20
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\opd = 20
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.endif
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.ifc \vxr,%v21
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\opd = 21
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.endif
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.ifc \vxr,%v22
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\opd = 22
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.endif
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.ifc \vxr,%v23
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\opd = 23
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.endif
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.ifc \vxr,%v24
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\opd = 24
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.endif
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.ifc \vxr,%v25
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\opd = 25
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.endif
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.ifc \vxr,%v26
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\opd = 26
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.endif
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.ifc \vxr,%v27
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\opd = 27
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.endif
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.ifc \vxr,%v28
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\opd = 28
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.endif
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.ifc \vxr,%v29
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\opd = 29
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.endif
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.ifc \vxr,%v30
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\opd = 30
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.endif
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.ifc \vxr,%v31
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\opd = 31
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.endif
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2016-08-25 15:40:19 +07:00
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.if \opd == 255
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\opd = \vxr
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2015-03-30 22:32:52 +07:00
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.endif
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.endm
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/* RXB - Compute most significant bit used vector registers
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*
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* @rxb: Operand to store computed RXB value
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* @v1: First vector register designated operand
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* @v2: Second vector register designated operand
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* @v3: Third vector register designated operand
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* @v4: Fourth vector register designated operand
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*/
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.macro RXB rxb v1 v2=0 v3=0 v4=0
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\rxb = 0
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.if \v1 & 0x10
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\rxb = \rxb | 0x08
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.endif
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.if \v2 & 0x10
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\rxb = \rxb | 0x04
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.endif
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.if \v3 & 0x10
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\rxb = \rxb | 0x02
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.endif
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.if \v4 & 0x10
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\rxb = \rxb | 0x01
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.endif
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.endm
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/* MRXB - Generate Element Size Control and RXB value
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*
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* @m: Element size control
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* @v1: First vector register designated operand (for RXB)
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* @v2: Second vector register designated operand (for RXB)
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* @v3: Third vector register designated operand (for RXB)
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* @v4: Fourth vector register designated operand (for RXB)
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*/
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.macro MRXB m v1 v2=0 v3=0 v4=0
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rxb = 0
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RXB rxb, \v1, \v2, \v3, \v4
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.byte (\m << 4) | rxb
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.endm
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/* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
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*
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* @m: Element size control
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* @opc: Opcode
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* @v1: First vector register designated operand (for RXB)
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* @v2: Second vector register designated operand (for RXB)
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* @v3: Third vector register designated operand (for RXB)
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* @v4: Fourth vector register designated operand (for RXB)
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*/
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.macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
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MRXB \m, \v1, \v2, \v3, \v4
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.byte \opc
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.endm
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/* Vector support instructions */
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/* VECTOR GENERATE BYTE MASK */
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.macro VGBM vr imm2
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VX_NUM v1, \vr
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2016-08-25 15:40:19 +07:00
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.word (0xE700 | ((v1&15) << 4))
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2015-03-30 22:32:52 +07:00
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.word \imm2
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MRXBOPC 0, 0x44, v1
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.endm
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.macro VZERO vxr
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VGBM \vxr, 0
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.endm
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.macro VONE vxr
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VGBM \vxr, 0xFFFF
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.endm
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/* VECTOR LOAD VR ELEMENT FROM GR */
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.macro VLVG v, gr, disp, m
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VX_NUM v1, \v
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GR_NUM b2, "%r0"
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GR_NUM r3, \gr
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2016-08-25 15:40:19 +07:00
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|
.word 0xE700 | ((v1&15) << 4) | r3
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC \m, 0x22, v1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLVGB v, gr, index, base
|
|
|
|
|
VLVG \v, \gr, \index, \base, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLVGH v, gr, index
|
|
|
|
|
VLVG \v, \gr, \index, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLVGF v, gr, index
|
|
|
|
|
VLVG \v, \gr, \index, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLVGG v, gr, index
|
|
|
|
|
VLVG \v, \gr, \index, 3
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-08-23 18:30:24 +07:00
|
|
|
/* VECTOR LOAD REGISTER */
|
|
|
|
|
.macro VLR v1, v2
|
|
|
|
|
VX_NUM v1, \v1
|
|
|
|
|
VX_NUM v2, \v2
|
|
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word 0
|
|
|
|
|
MRXBOPC 0, 0x56, v1, v2
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-03-30 22:32:52 +07:00
|
|
|
/* VECTOR LOAD */
|
|
|
|
|
.macro VL v, disp, index="%r0", base
|
|
|
|
|
VX_NUM v1, \v
|
|
|
|
|
GR_NUM x2, \index
|
|
|
|
|
GR_NUM b2, \base
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | x2
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC 0, 0x06, v1
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR LOAD ELEMENT */
|
|
|
|
|
.macro VLEx vr1, disp, index="%r0", base, m3, opc
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
GR_NUM x2, \index
|
|
|
|
|
GR_NUM b2, \base
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | x2
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC \m3, \opc, v1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEB vr1, disp, index="%r0", base, m3
|
|
|
|
|
VLEx \vr1, \disp, \index, \base, \m3, 0x00
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEH vr1, disp, index="%r0", base, m3
|
|
|
|
|
VLEx \vr1, \disp, \index, \base, \m3, 0x01
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEF vr1, disp, index="%r0", base, m3
|
|
|
|
|
VLEx \vr1, \disp, \index, \base, \m3, 0x03
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEG vr1, disp, index="%r0", base, m3
|
|
|
|
|
VLEx \vr1, \disp, \index, \base, \m3, 0x02
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR LOAD ELEMENT IMMEDIATE */
|
|
|
|
|
.macro VLEIx vr1, imm2, m3, opc
|
|
|
|
|
VX_NUM v1, \vr1
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4)
|
2015-03-30 22:32:52 +07:00
|
|
|
.word \imm2
|
|
|
|
|
MRXBOPC \m3, \opc, v1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEIB vr1, imm2, index
|
|
|
|
|
VLEIx \vr1, \imm2, \index, 0x40
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEIH vr1, imm2, index
|
|
|
|
|
VLEIx \vr1, \imm2, \index, 0x41
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEIF vr1, imm2, index
|
|
|
|
|
VLEIx \vr1, \imm2, \index, 0x43
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLEIG vr1, imm2, index
|
|
|
|
|
VLEIx \vr1, \imm2, \index, 0x42
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR LOAD GR FROM VR ELEMENT */
|
|
|
|
|
.macro VLGV gr, vr, disp, base="%r0", m
|
|
|
|
|
GR_NUM r1, \gr
|
|
|
|
|
GR_NUM b2, \base
|
|
|
|
|
VX_NUM v3, \vr
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | (r1 << 4) | (v3&15)
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC \m, 0x21, v3
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLGVB gr, vr, disp, base="%r0"
|
|
|
|
|
VLGV \gr, \vr, \disp, \base, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLGVH gr, vr, disp, base="%r0"
|
|
|
|
|
VLGV \gr, \vr, \disp, \base, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLGVF gr, vr, disp, base="%r0"
|
|
|
|
|
VLGV \gr, \vr, \disp, \base, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VLGVG gr, vr, disp, base="%r0"
|
|
|
|
|
VLGV \gr, \vr, \disp, \base, 3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR LOAD MULTIPLE */
|
|
|
|
|
.macro VLM vfrom, vto, disp, base
|
|
|
|
|
VX_NUM v1, \vfrom
|
|
|
|
|
VX_NUM v3, \vto
|
|
|
|
|
GR_NUM b2, \base /* Base register */
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v3&15)
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC 0, 0x36, v1, v3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR STORE MULTIPLE */
|
|
|
|
|
.macro VSTM vfrom, vto, disp, base
|
|
|
|
|
VX_NUM v1, \vfrom
|
|
|
|
|
VX_NUM v3, \vto
|
|
|
|
|
GR_NUM b2, \base /* Base register */
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v3&15)
|
2015-03-30 22:32:52 +07:00
|
|
|
.word (b2 << 12) | (\disp)
|
|
|
|
|
MRXBOPC 0, 0x3E, v1, v3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR PERMUTE */
|
|
|
|
|
.macro VPERM vr1, vr2, vr3, vr4
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
|
|
|
|
VX_NUM v4, \vr4
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
|
|
|
|
MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4
|
2015-03-30 22:32:52 +07:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR UNPACK LOGICAL LOW */
|
|
|
|
|
.macro VUPLL vr1, vr2, m3
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
2015-03-30 22:32:52 +07:00
|
|
|
.word 0x0000
|
|
|
|
|
MRXBOPC \m3, 0xD4, v1, v2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VUPLLB vr1, vr2
|
|
|
|
|
VUPLL \vr1, \vr2, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VUPLLH vr1, vr2
|
|
|
|
|
VUPLL \vr1, \vr2, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VUPLLF vr1, vr2
|
|
|
|
|
VUPLL \vr1, \vr2, 2
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Vector integer instructions */
|
|
|
|
|
|
2016-08-23 18:30:24 +07:00
|
|
|
/* VECTOR AND */
|
|
|
|
|
.macro VN vr1, vr2, vr3
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
|
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
|
|
|
|
MRXBOPC 0, 0x68, v1, v2, v3
|
|
|
|
|
.endm
|
|
|
|
|
|
2015-03-30 22:32:52 +07:00
|
|
|
/* VECTOR EXCLUSIVE OR */
|
|
|
|
|
.macro VX vr1, vr2, vr3
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
2015-03-30 22:32:52 +07:00
|
|
|
MRXBOPC 0, 0x6D, v1, v2, v3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR GALOIS FIELD MULTIPLY SUM */
|
|
|
|
|
.macro VGFM vr1, vr2, vr3, m4
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
2015-03-30 22:32:52 +07:00
|
|
|
MRXBOPC \m4, 0xB4, v1, v2, v3
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMB vr1, vr2, vr3
|
|
|
|
|
VGFM \vr1, \vr2, \vr3, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMH vr1, vr2, vr3
|
|
|
|
|
VGFM \vr1, \vr2, \vr3, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMF vr1, vr2, vr3
|
|
|
|
|
VGFM \vr1, \vr2, \vr3, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMG vr1, vr2, vr3
|
|
|
|
|
VGFM \vr1, \vr2, \vr3, 3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
|
|
|
|
|
.macro VGFMA vr1, vr2, vr3, vr4, m5
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
|
|
|
|
VX_NUM v4, \vr4
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12) | (\m5 << 8)
|
|
|
|
|
MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4
|
2015-03-30 22:32:52 +07:00
|
|
|
.endm
|
|
|
|
|
.macro VGFMAB vr1, vr2, vr3, vr4
|
|
|
|
|
VGFMA \vr1, \vr2, \vr3, \vr4, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMAH vr1, vr2, vr3, vr4
|
|
|
|
|
VGFMA \vr1, \vr2, \vr3, \vr4, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMAF vr1, vr2, vr3, vr4
|
|
|
|
|
VGFMA \vr1, \vr2, \vr3, \vr4, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VGFMAG vr1, vr2, vr3, vr4
|
|
|
|
|
VGFMA \vr1, \vr2, \vr3, \vr4, 3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
|
|
|
|
|
.macro VSRLB vr1, vr2, vr3
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
2016-08-25 15:40:19 +07:00
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
2015-03-30 22:32:52 +07:00
|
|
|
MRXBOPC 0, 0x7D, v1, v2, v3
|
|
|
|
|
.endm
|
|
|
|
|
|
2016-08-23 18:30:24 +07:00
|
|
|
/* VECTOR REPLICATE IMMEDIATE */
|
|
|
|
|
.macro VREPI vr1, imm2, m3
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
.word 0xE700 | ((v1&15) << 4)
|
|
|
|
|
.word \imm2
|
|
|
|
|
MRXBOPC \m3, 0x45, v1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VREPIB vr1, imm2
|
|
|
|
|
VREPI \vr1, \imm2, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VREPIH vr1, imm2
|
|
|
|
|
VREPI \vr1, \imm2, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VREPIF vr1, imm2
|
|
|
|
|
VREPI \vr1, \imm2, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VREPIG vr1, imm2
|
|
|
|
|
VREP \vr1, \imm2, 3
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR ADD */
|
|
|
|
|
.macro VA vr1, vr2, vr3, m4
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
|
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
|
|
|
|
MRXBOPC \m4, 0xF3, v1, v2, v3
|
|
|
|
|
.endm
|
|
|
|
|
.macro VAB vr1, vr2, vr3
|
|
|
|
|
VA \vr1, \vr2, \vr3, 0
|
|
|
|
|
.endm
|
|
|
|
|
.macro VAH vr1, vr2, vr3
|
|
|
|
|
VA \vr1, \vr2, \vr3, 1
|
|
|
|
|
.endm
|
|
|
|
|
.macro VAF vr1, vr2, vr3
|
|
|
|
|
VA \vr1, \vr2, \vr3, 2
|
|
|
|
|
.endm
|
|
|
|
|
.macro VAG vr1, vr2, vr3
|
|
|
|
|
VA \vr1, \vr2, \vr3, 3
|
|
|
|
|
.endm
|
|
|
|
|
.macro VAQ vr1, vr2, vr3
|
|
|
|
|
VA \vr1, \vr2, \vr3, 4
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
|
|
|
|
|
.macro VESRAV vr1, vr2, vr3, m4
|
|
|
|
|
VX_NUM v1, \vr1
|
|
|
|
|
VX_NUM v2, \vr2
|
|
|
|
|
VX_NUM v3, \vr3
|
|
|
|
|
.word 0xE700 | ((v1&15) << 4) | (v2&15)
|
|
|
|
|
.word ((v3&15) << 12)
|
|
|
|
|
MRXBOPC \m4, 0x7A, v1, v2, v3
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.endm
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.macro VESRAVB vr1, vr2, vr3
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VESRAV \vr1, \vr2, \vr3, 0
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.endm
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.macro VESRAVH vr1, vr2, vr3
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VESRAV \vr1, \vr2, \vr3, 1
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.endm
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.macro VESRAVF vr1, vr2, vr3
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VESRAV \vr1, \vr2, \vr3, 2
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.endm
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.macro VESRAVG vr1, vr2, vr3
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VESRAV \vr1, \vr2, \vr3, 3
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.endm
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2015-03-30 22:32:52 +07:00
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_S390_VX_INSN_H */
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