2005-11-04 07:50:04 +07:00
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/*
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2005-04-17 05:20:36 +07:00
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* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
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2012-02-28 03:03:51 +07:00
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* Copyright 2001-2012 IBM Corporation.
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2005-04-17 05:20:36 +07:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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2005-11-04 07:50:04 +07:00
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*
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2005-04-17 05:20:36 +07:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2005-11-04 07:50:04 +07:00
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*
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2005-04-17 05:20:36 +07:00
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2008-10-28 02:48:37 +07:00
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#ifndef _POWERPC_EEH_H
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#define _POWERPC_EEH_H
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2005-12-17 04:43:46 +07:00
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#ifdef __KERNEL__
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2005-04-17 05:20:36 +07:00
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/string.h>
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2013-06-20 12:21:01 +07:00
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#include <linux/time.h>
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2005-04-17 05:20:36 +07:00
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struct pci_dev;
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2006-02-25 00:34:23 +07:00
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struct pci_bus;
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2005-04-17 05:20:36 +07:00
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struct device_node;
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#ifdef CONFIG_EEH
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2014-04-24 15:00:17 +07:00
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/* EEH subsystem flags */
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#define EEH_ENABLED 0x1 /* EEH enabled */
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#define EEH_FORCE_DISABLED 0x2 /* EEH disabled */
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#define EEH_PROBE_MODE_DEV 0x4 /* From PCI device */
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#define EEH_PROBE_MODE_DEVTREE 0x8 /* From device tree */
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2014-04-24 15:00:23 +07:00
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/*
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* Delay for PE reset, all in ms
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*
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* PCI specification has reset hold time of 100 milliseconds.
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* We have 250 milliseconds here. The PCI bus settlement time
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* is specified as 1.5 seconds and we have 1.8 seconds.
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*/
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#define EEH_PE_RST_HOLD_TIME 250
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#define EEH_PE_RST_SETTLE_TIME 1800
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2012-09-08 05:44:05 +07:00
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/*
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* The struct is used to trace PE related EEH functionality.
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* In theory, there will have one instance of the struct to
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* be created against particular PE. In nature, PEs corelate
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* to each other. the struct has to reflect that hierarchy in
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* order to easily pick up those affected PEs when one particular
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* PE has EEH errors.
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*
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* Also, one particular PE might be composed of PCI device, PCI
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* bus and its subordinate components. The struct also need ship
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* the information. Further more, one particular PE is only meaingful
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* in the corresponding PHB. Therefore, the root PEs should be created
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* against existing PHBs in on-to-one fashion.
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*/
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2012-09-12 02:16:16 +07:00
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#define EEH_PE_INVALID (1 << 0) /* Invalid */
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#define EEH_PE_PHB (1 << 1) /* PHB PE */
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#define EEH_PE_DEVICE (1 << 2) /* Device PE */
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#define EEH_PE_BUS (1 << 3) /* Bus PE */
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2012-09-08 05:44:05 +07:00
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#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
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#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
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2014-04-24 15:00:12 +07:00
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#define EEH_PE_RESET (1 << 2) /* PE reset in progress */
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2012-09-08 05:44:05 +07:00
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2013-07-24 09:24:55 +07:00
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#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
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2012-09-08 05:44:05 +07:00
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struct eeh_pe {
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int type; /* PE type: PHB/Bus/Device */
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int state; /* PE EEH dependent mode */
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int config_addr; /* Traditional PCI address */
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int addr; /* PE configuration address */
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struct pci_controller *phb; /* Associated PHB */
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2013-06-20 12:20:55 +07:00
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struct pci_bus *bus; /* Top PCI bus for bus PE */
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2012-09-08 05:44:05 +07:00
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int check_count; /* Times of ignored error */
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int freeze_count; /* Times of froze up */
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2013-06-20 12:21:01 +07:00
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struct timeval tstamp; /* Time on first-time freeze */
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2012-09-08 05:44:05 +07:00
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int false_positives; /* Times of reported #ff's */
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struct eeh_pe *parent; /* Parent PE */
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struct list_head child_list; /* Link PE to the child list */
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struct list_head edevs; /* Link list of EEH devices */
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struct list_head child; /* Child PEs */
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};
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2013-07-24 09:24:56 +07:00
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#define eeh_pe_for_each_dev(pe, edev, tmp) \
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list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
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2012-09-08 05:44:12 +07:00
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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/*
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* The struct is used to trace EEH state for the associated
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* PCI device node or PCI device. In future, it might
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* represent PE as well so that the EEH device to form
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* another tree except the currently existing tree of PCI
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* buses and PCI devices
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*/
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2013-07-24 09:24:59 +07:00
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#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
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#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
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#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
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#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
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#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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2014-01-12 13:13:45 +07:00
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#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
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#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
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powerpc/eeh: No hotplug on permanently removed dev
The issue was detected in a bit complicated test case where
we have multiple hierarchical PEs shown as following figure:
+-----------------+
| PE#3 p2p#0 |
| p2p#1 |
+-----------------+
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+-----------------+
| PE#4 pdev#0 |
| pdev#1 |
+-----------------+
PE#4 (have 2 PCI devices) is the child of PE#3, which has 2 p2p
bridges. We accidentally had less-known scenario: PE#4 was removed
permanently from the system because of permanent failure (e.g.
exceeding the max allowd failure times in last hour), then we detects
EEH errors on PE#3 and tried to recover it. However, eeh_dev instances
for pdev#0/1 were not detached from PE#4, which was still connected to
PE#3. All of that was because of the fact that we rely on count-based
pcibios_release_device(), which isn't reliable enough. When doing
recovery for PE#3, we still apply hotplug on PE#4 and pdev#0/1, which
are not valid any more. Eventually, we run into kernel crash.
The patch fixes above issue from two aspects. For unplug, we simply
skip those permanently removed PE, whose state is (EEH_PE_STATE_ISOLATED
&& !EEH_PE_STATE_RECOVERING) and its frozen count should be greater
than EEH_MAX_ALLOWED_FREEZES. For plug, we marked all permanently
removed EEH devices with EEH_DEV_REMOVED and return 0xFF's on read
its PCI config so that PCI core will omit them.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-04-24 15:00:19 +07:00
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#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
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2013-07-24 09:25:01 +07:00
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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struct eeh_dev {
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int mode; /* EEH mode */
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int class_code; /* Class code of the device */
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int config_addr; /* Config address */
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int pe_config_addr; /* PE config address */
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u32 config_space[16]; /* Saved PCI config space */
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2014-04-24 15:00:16 +07:00
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int pcix_cap; /* Saved PCIx capability */
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int pcie_cap; /* Saved PCIe capability */
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int aer_cap; /* Saved AER capability */
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2012-09-08 05:44:05 +07:00
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struct eeh_pe *pe; /* Associated PE */
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struct list_head list; /* Form link list in the PE */
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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struct pci_controller *phb; /* Associated PHB */
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struct device_node *dn; /* Associated device node */
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struct pci_dev *pdev; /* Associated PCI device */
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powerpc/eeh: Use partial hotplug for EEH unaware drivers
When EEH error happens to one specific PE, some devices with drivers
supporting EEH won't except hotplug on the device. However, there
might have other deivces without driver, or with driver without EEH
support. For the case, we need do partial hotplug in order to make
sure that the PE becomes absolutely quite during reset. Otherise,
the PE reset might fail and leads to failure of error recovery.
The current code doesn't handle that 'mixed' case properly, it either
uses the error callbacks to the drivers, or tries hotplug, but doesn't
handle a PE (EEH domain) composed of a combination of the two.
The patch intends to support so-called "partial" hotplug for EEH:
Before we do reset, we stop and remove those PCI devices without
EEH sensitive driver. The corresponding EEH devices are not detached
from its PE, but with special flag. After the reset is done, those
EEH devices with the special flag will be scanned one by one.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-24 09:24:58 +07:00
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struct pci_bus *bus; /* PCI bus for partial hotplug */
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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};
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static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
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{
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2013-06-05 14:34:03 +07:00
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return edev ? edev->dn : NULL;
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powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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}
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static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
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{
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2013-06-05 14:34:03 +07:00
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return edev ? edev->pdev : NULL;
|
powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
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}
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2014-01-15 12:16:11 +07:00
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/* Return values from eeh_ops::next_error */
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enum {
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EEH_NEXT_ERR_NONE = 0,
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EEH_NEXT_ERR_INF,
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EEH_NEXT_ERR_FROZEN_PE,
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EEH_NEXT_ERR_FENCED_PHB,
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EEH_NEXT_ERR_DEAD_PHB,
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EEH_NEXT_ERR_DEAD_IOC
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};
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2012-02-28 03:03:53 +07:00
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/*
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* The struct is used to trace the registered EEH operation
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* callback functions. Actually, those operation callback
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* functions are heavily platform dependent. That means the
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* platform should register its own EEH operation callback
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* functions before any EEH further operations.
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*/
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2012-02-28 03:03:55 +07:00
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#define EEH_OPT_DISABLE 0 /* EEH disable */
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#define EEH_OPT_ENABLE 1 /* EEH enable */
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#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
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#define EEH_OPT_THAW_DMA 3 /* DMA enable */
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2012-02-28 03:03:57 +07:00
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#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
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#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
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|
|
|
#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
|
|
|
|
#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
|
|
|
|
#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
|
|
|
|
#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
|
|
|
|
#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
|
2012-02-28 03:03:59 +07:00
|
|
|
#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
|
|
|
|
#define EEH_RESET_HOT 1 /* Hot reset */
|
|
|
|
#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
|
2012-02-28 03:04:00 +07:00
|
|
|
#define EEH_LOG_TEMP 1 /* EEH temporary error log */
|
|
|
|
#define EEH_LOG_PERM 2 /* EEH permanent error log */
|
2012-02-28 03:03:57 +07:00
|
|
|
|
2012-02-28 03:03:53 +07:00
|
|
|
struct eeh_ops {
|
|
|
|
char *name;
|
|
|
|
int (*init)(void);
|
2013-06-20 12:20:57 +07:00
|
|
|
int (*post_init)(void);
|
2012-09-08 05:44:21 +07:00
|
|
|
void* (*of_probe)(struct device_node *dn, void *flag);
|
2013-06-20 12:20:56 +07:00
|
|
|
int (*dev_probe)(struct pci_dev *dev, void *flag);
|
2012-09-08 05:44:14 +07:00
|
|
|
int (*set_option)(struct eeh_pe *pe, int option);
|
|
|
|
int (*get_pe_addr)(struct eeh_pe *pe);
|
|
|
|
int (*get_state)(struct eeh_pe *pe, int *state);
|
|
|
|
int (*reset)(struct eeh_pe *pe, int option);
|
|
|
|
int (*wait_state)(struct eeh_pe *pe, int max_wait);
|
|
|
|
int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
|
|
|
|
int (*configure_bridge)(struct eeh_pe *pe);
|
2012-02-28 03:04:11 +07:00
|
|
|
int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
|
|
|
|
int (*write_config)(struct device_node *dn, int where, int size, u32 val);
|
2013-06-20 12:21:04 +07:00
|
|
|
int (*next_error)(struct eeh_pe **pe);
|
2014-01-03 16:47:12 +07:00
|
|
|
int (*restore_config)(struct device_node *dn);
|
2012-02-28 03:03:53 +07:00
|
|
|
};
|
|
|
|
|
2014-04-24 15:00:17 +07:00
|
|
|
extern int eeh_subsystem_flags;
|
2012-02-28 03:03:53 +07:00
|
|
|
extern struct eeh_ops *eeh_ops;
|
2013-06-20 12:21:03 +07:00
|
|
|
extern raw_spinlock_t confirm_error_lock;
|
2012-09-08 05:44:21 +07:00
|
|
|
|
2014-02-12 14:24:55 +07:00
|
|
|
static inline bool eeh_enabled(void)
|
|
|
|
{
|
2014-04-24 15:00:17 +07:00
|
|
|
if ((eeh_subsystem_flags & EEH_FORCE_DISABLED) ||
|
|
|
|
!(eeh_subsystem_flags & EEH_ENABLED))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
2014-02-12 14:24:55 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void eeh_set_enable(bool mode)
|
|
|
|
{
|
2014-04-24 15:00:17 +07:00
|
|
|
if (mode)
|
|
|
|
eeh_subsystem_flags |= EEH_ENABLED;
|
|
|
|
else
|
|
|
|
eeh_subsystem_flags &= ~EEH_ENABLED;
|
2014-02-12 14:24:55 +07:00
|
|
|
}
|
|
|
|
|
2012-09-08 05:44:21 +07:00
|
|
|
static inline void eeh_probe_mode_set(int flag)
|
|
|
|
{
|
2014-04-24 15:00:17 +07:00
|
|
|
eeh_subsystem_flags |= flag;
|
2012-09-08 05:44:21 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int eeh_probe_mode_devtree(void)
|
|
|
|
{
|
2014-04-24 15:00:17 +07:00
|
|
|
return (eeh_subsystem_flags & EEH_PROBE_MODE_DEVTREE);
|
2012-09-08 05:44:21 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int eeh_probe_mode_dev(void)
|
|
|
|
{
|
2014-04-24 15:00:17 +07:00
|
|
|
return (eeh_subsystem_flags & EEH_PROBE_MODE_DEV);
|
2012-09-08 05:44:21 +07:00
|
|
|
}
|
2012-09-08 05:44:06 +07:00
|
|
|
|
2013-06-20 12:21:03 +07:00
|
|
|
static inline void eeh_serialize_lock(unsigned long *flags)
|
|
|
|
{
|
|
|
|
raw_spin_lock_irqsave(&confirm_error_lock, *flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void eeh_serialize_unlock(unsigned long flags)
|
|
|
|
{
|
|
|
|
raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
|
|
|
|
}
|
|
|
|
|
2012-02-28 03:03:51 +07:00
|
|
|
/*
|
|
|
|
* Max number of EEH freezes allowed before we consider the device
|
|
|
|
* to be permanently disabled.
|
|
|
|
*/
|
2005-11-04 07:50:04 +07:00
|
|
|
#define EEH_MAX_ALLOWED_FREEZES 5
|
|
|
|
|
2012-09-08 05:44:08 +07:00
|
|
|
typedef void *(*eeh_traverse_func)(void *data, void *flag);
|
2012-12-22 05:04:10 +07:00
|
|
|
int eeh_phb_pe_create(struct pci_controller *phb);
|
2013-06-20 12:20:53 +07:00
|
|
|
struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
|
2013-06-20 12:20:54 +07:00
|
|
|
struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
|
2012-09-08 05:44:09 +07:00
|
|
|
int eeh_add_to_parent_pe(struct eeh_dev *edev);
|
2013-07-24 09:24:55 +07:00
|
|
|
int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
|
2013-06-20 12:21:01 +07:00
|
|
|
void eeh_pe_update_time_stamp(struct eeh_pe *pe);
|
powerpc/eeh: Use partial hotplug for EEH unaware drivers
When EEH error happens to one specific PE, some devices with drivers
supporting EEH won't except hotplug on the device. However, there
might have other deivces without driver, or with driver without EEH
support. For the case, we need do partial hotplug in order to make
sure that the PE becomes absolutely quite during reset. Otherise,
the PE reset might fail and leads to failure of error recovery.
The current code doesn't handle that 'mixed' case properly, it either
uses the error callbacks to the drivers, or tries hotplug, but doesn't
handle a PE (EEH domain) composed of a combination of the two.
The patch intends to support so-called "partial" hotplug for EEH:
Before we do reset, we stop and remove those PCI devices without
EEH sensitive driver. The corresponding EEH devices are not detached
from its PE, but with special flag. After the reset is done, those
EEH devices with the special flag will be scanned one by one.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-24 09:24:58 +07:00
|
|
|
void *eeh_pe_traverse(struct eeh_pe *root,
|
|
|
|
eeh_traverse_func fn, void *flag);
|
2012-09-08 05:44:15 +07:00
|
|
|
void *eeh_pe_dev_traverse(struct eeh_pe *root,
|
|
|
|
eeh_traverse_func fn, void *flag);
|
|
|
|
void eeh_pe_restore_bars(struct eeh_pe *pe);
|
2012-09-08 05:44:19 +07:00
|
|
|
struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
|
2012-09-08 05:44:07 +07:00
|
|
|
|
2012-12-22 05:04:10 +07:00
|
|
|
void *eeh_dev_init(struct device_node *dn, void *data);
|
|
|
|
void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
|
2013-06-27 12:46:47 +07:00
|
|
|
int eeh_init(void);
|
2012-02-28 03:03:53 +07:00
|
|
|
int __init eeh_ops_register(struct eeh_ops *ops);
|
|
|
|
int __exit eeh_ops_unregister(const char *name);
|
2005-04-17 05:20:36 +07:00
|
|
|
unsigned long eeh_check_failure(const volatile void __iomem *token,
|
|
|
|
unsigned long val);
|
2012-09-08 05:44:22 +07:00
|
|
|
int eeh_dev_check_failure(struct eeh_dev *edev);
|
2013-06-27 12:46:47 +07:00
|
|
|
void eeh_addr_cache_build(void);
|
2013-07-24 09:24:52 +07:00
|
|
|
void eeh_add_device_early(struct device_node *);
|
2005-11-04 07:51:31 +07:00
|
|
|
void eeh_add_device_tree_early(struct device_node *);
|
2013-07-24 09:24:52 +07:00
|
|
|
void eeh_add_device_late(struct pci_dev *);
|
2006-02-25 00:34:23 +07:00
|
|
|
void eeh_add_device_tree_late(struct pci_bus *);
|
2012-12-28 16:13:19 +07:00
|
|
|
void eeh_add_sysfs_files(struct pci_bus *);
|
2013-07-24 09:24:55 +07:00
|
|
|
void eeh_remove_device(struct pci_dev *);
|
2005-11-04 07:51:31 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
|
|
|
* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
|
|
|
|
*
|
|
|
|
* If this macro yields TRUE, the caller relays to eeh_check_failure()
|
|
|
|
* which does further tests out of line.
|
|
|
|
*/
|
2014-02-12 14:24:55 +07:00
|
|
|
#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Reads from a device which has been isolated by EEH will return
|
|
|
|
* all 1s. This macro gives an all-1s value of the given size (in
|
|
|
|
* bytes: 1, 2, or 4) for comparing with the result of a read.
|
|
|
|
*/
|
|
|
|
#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
|
|
|
|
|
|
|
|
#else /* !CONFIG_EEH */
|
powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
|
|
|
|
2014-02-12 14:24:55 +07:00
|
|
|
static inline bool eeh_enabled(void)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void eeh_set_enable(bool mode) { }
|
|
|
|
|
2013-06-20 12:20:56 +07:00
|
|
|
static inline int eeh_init(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
|
|
|
static inline void *eeh_dev_init(struct device_node *dn, void *data)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
|
|
|
|
{
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-09-08 05:44:22 +07:00
|
|
|
#define eeh_dev_check_failure(x) (0)
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-09-08 05:44:23 +07:00
|
|
|
static inline void eeh_addr_cache_build(void) { }
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-07-24 09:24:52 +07:00
|
|
|
static inline void eeh_add_device_early(struct device_node *dn) { }
|
|
|
|
|
2005-12-28 09:58:29 +07:00
|
|
|
static inline void eeh_add_device_tree_early(struct device_node *dn) { }
|
|
|
|
|
2013-07-24 09:24:52 +07:00
|
|
|
static inline void eeh_add_device_late(struct pci_dev *dev) { }
|
|
|
|
|
2006-02-25 00:34:23 +07:00
|
|
|
static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
|
|
|
|
|
2012-12-28 16:13:19 +07:00
|
|
|
static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
|
|
|
|
|
2013-07-24 09:24:55 +07:00
|
|
|
static inline void eeh_remove_device(struct pci_dev *dev) { }
|
2012-09-08 05:44:06 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#define EEH_POSSIBLE_ERROR(val, type) (0)
|
|
|
|
#define EEH_IO_ERROR_VALUE(size) (-1UL)
|
|
|
|
#endif /* CONFIG_EEH */
|
|
|
|
|
2008-10-28 02:48:37 +07:00
|
|
|
#ifdef CONFIG_PPC64
|
2005-11-04 07:50:04 +07:00
|
|
|
/*
|
2005-04-17 05:20:36 +07:00
|
|
|
* MMIO read/write operations with EEH support.
|
|
|
|
*/
|
|
|
|
static inline u8 eeh_readb(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
u8 val = in_8(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u8))
|
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u16 eeh_readw(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
u16 val = in_le16(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u16))
|
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 eeh_readl(const volatile void __iomem *addr)
|
|
|
|
{
|
|
|
|
u32 val = in_le32(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u32))
|
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
|
|
|
|
static inline u64 eeh_readq(const volatile void __iomem *addr)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
u64 val = in_le64(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u64))
|
2005-04-17 05:20:36 +07:00
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
static inline u16 eeh_readw_be(const volatile void __iomem *addr)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
u16 val = in_be16(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u16))
|
2005-04-17 05:20:36 +07:00
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
|
|
|
|
static inline u32 eeh_readl_be(const volatile void __iomem *addr)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
u32 val = in_be32(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u32))
|
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
|
|
|
|
static inline u64 eeh_readq_be(const volatile void __iomem *addr)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
u64 val = in_be64(addr);
|
|
|
|
if (EEH_POSSIBLE_ERROR(val, u64))
|
|
|
|
return eeh_check_failure(addr, val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2006-11-13 05:27:39 +07:00
|
|
|
static inline void eeh_memcpy_fromio(void *dest, const
|
|
|
|
volatile void __iomem *src,
|
2005-04-17 05:20:36 +07:00
|
|
|
unsigned long n)
|
|
|
|
{
|
2006-11-13 05:27:39 +07:00
|
|
|
_memcpy_fromio(dest, src, n);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
|
|
|
|
* were copied. Check all four bytes.
|
|
|
|
*/
|
2006-11-13 05:27:39 +07:00
|
|
|
if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
|
|
|
|
eeh_check_failure(src, *((u32 *)(dest + n - 4)));
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* in-string eeh macros */
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
|
|
|
|
int ns)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
_insb(addr, buf, ns);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
eeh_check_failure(addr, *(u8*)buf);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
|
|
|
|
int ns)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
_insw(addr, buf, ns);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
eeh_check_failure(addr, *(u16*)buf);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
|
|
|
|
int nl)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
|
|
|
_insl(addr, buf, nl);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
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[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 13:25:10 +07:00
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eeh_check_failure(addr, *(u32*)buf);
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2005-04-17 05:20:36 +07:00
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}
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2008-10-28 02:48:37 +07:00
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#endif /* CONFIG_PPC64 */
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2005-12-17 04:43:46 +07:00
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#endif /* __KERNEL__ */
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2008-10-28 02:48:37 +07:00
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#endif /* _POWERPC_EEH_H */
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