2018-01-27 01:50:27 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2015-04-09 01:21:35 +07:00
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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2018-05-12 00:15:30 +07:00
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#include "../pci.h"
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2015-04-09 01:21:35 +07:00
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#include "pcie-iproc.h"
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2015-12-05 00:34:59 +07:00
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static const struct of_device_id iproc_pcie_of_match_table[] = {
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{
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.compatible = "brcm,iproc-pcie",
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.data = (int *)IPROC_PCIE_PAXB,
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2016-11-01 07:38:41 +07:00
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}, {
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.compatible = "brcm,iproc-pcie-paxb-v2",
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.data = (int *)IPROC_PCIE_PAXB_V2,
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2015-12-05 00:34:59 +07:00
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}, {
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.compatible = "brcm,iproc-pcie-paxc",
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.data = (int *)IPROC_PCIE_PAXC,
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2016-11-01 07:38:35 +07:00
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}, {
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.compatible = "brcm,iproc-pcie-paxc-v2",
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.data = (int *)IPROC_PCIE_PAXC_V2,
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2015-12-05 00:34:59 +07:00
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
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2015-04-09 01:21:35 +07:00
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static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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{
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2016-10-07 01:36:08 +07:00
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struct device *dev = &pdev->dev;
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2015-04-09 01:21:35 +07:00
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struct iproc_pcie *pcie;
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2016-10-07 01:36:08 +07:00
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struct device_node *np = dev->of_node;
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2015-04-09 01:21:35 +07:00
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struct resource reg;
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2017-06-29 03:13:57 +07:00
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struct pci_host_bridge *bridge;
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2015-04-09 01:21:35 +07:00
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int ret;
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2017-06-29 03:13:57 +07:00
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
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if (!bridge)
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2015-04-09 01:21:35 +07:00
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return -ENOMEM;
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2017-06-29 03:13:57 +07:00
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pcie = pci_host_bridge_priv(bridge);
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2016-10-07 01:36:08 +07:00
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pcie->dev = dev;
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2017-02-01 05:36:32 +07:00
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pcie->type = (enum iproc_pcie_type) of_device_get_match_data(dev);
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2015-04-09 01:21:35 +07:00
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ret = of_address_to_resource(np, 0, ®);
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if (ret < 0) {
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2016-10-07 01:36:08 +07:00
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dev_err(dev, "unable to obtain controller resources\n");
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2015-04-09 01:21:35 +07:00
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return ret;
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}
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2017-04-19 23:49:02 +07:00
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pcie->base = devm_pci_remap_cfgspace(dev, reg.start,
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resource_size(®));
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2015-04-09 01:21:35 +07:00
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if (!pcie->base) {
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2016-10-07 01:36:08 +07:00
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dev_err(dev, "unable to map controller registers\n");
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2015-04-09 01:21:35 +07:00
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return -ENOMEM;
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}
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2016-01-07 07:04:35 +07:00
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pcie->base_addr = reg.start;
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2015-04-09 01:21:35 +07:00
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2015-10-16 20:18:24 +07:00
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if (of_property_read_bool(np, "brcm,pcie-ob")) {
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u32 val;
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ret = of_property_read_u32(np, "brcm,pcie-ob-axi-offset",
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&val);
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if (ret) {
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2016-10-07 01:36:08 +07:00
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dev_err(dev,
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2015-10-16 20:18:24 +07:00
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"missing brcm,pcie-ob-axi-offset property\n");
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return ret;
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}
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pcie->ob.axi_offset = val;
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pcie->need_ob_cfg = true;
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}
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2018-01-12 03:36:16 +07:00
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/*
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* DT nodes are not used by all platforms that use the iProc PCIe
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2019-05-30 20:05:58 +07:00
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* core driver. For platforms that require explicit inbound mapping
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2018-01-12 03:36:16 +07:00
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* configuration, "dma-ranges" would have been present in DT
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*/
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pcie->need_ib_cfg = of_property_read_bool(np, "dma-ranges");
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2015-04-09 01:21:35 +07:00
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/* PHY use is optional */
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2019-08-29 17:53:19 +07:00
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pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
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if (IS_ERR(pcie->phy))
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return PTR_ERR(pcie->phy);
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2015-04-09 01:21:35 +07:00
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2019-10-31 05:30:57 +07:00
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ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
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&bridge->dma_ranges, NULL);
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2015-04-09 01:21:35 +07:00
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if (ret) {
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2017-03-10 00:27:07 +07:00
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dev_err(dev, "unable to get PCI host bridge resources\n");
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2015-04-09 01:21:35 +07:00
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return ret;
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}
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2016-12-02 03:34:52 +07:00
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/* PAXC doesn't support legacy IRQs, skip mapping */
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switch (pcie->type) {
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case IPROC_PCIE_PAXC:
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case IPROC_PCIE_PAXC_V2:
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break;
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default:
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pcie->map_irq = of_irq_parse_and_map_pci;
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}
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2015-05-13 04:23:00 +07:00
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2019-10-28 23:32:38 +07:00
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ret = iproc_pcie_setup(pcie, &bridge->windows);
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2017-03-10 00:27:07 +07:00
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if (ret) {
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2016-10-07 01:36:08 +07:00
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dev_err(dev, "PCIe controller setup failed\n");
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2017-03-10 00:27:07 +07:00
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return ret;
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}
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2015-05-25 03:37:03 +07:00
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2016-10-07 01:36:08 +07:00
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platform_set_drvdata(pdev, pcie);
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2017-03-10 00:27:07 +07:00
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return 0;
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2015-04-09 01:21:35 +07:00
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}
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static int iproc_pcie_pltfm_remove(struct platform_device *pdev)
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{
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struct iproc_pcie *pcie = platform_get_drvdata(pdev);
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return iproc_pcie_remove(pcie);
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}
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PCI: iproc: Add 500ms delay during device shutdown
During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the
LCPLL clock and PERST both go off simultaneously. This seems in accordance
with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the
clock goes inactive after PERST# goes active, but doesn't specify how long
the clock should be valid after PERST#.
However, we have observed that with the iProc Stingray, some Intel NVMe
endpoints, e.g., the P3700 400GB series, are not detected correctly upon
the next boot sequence unless the clock remains valid for some time after
PERST# is asserted.
Delay 500ms after asserting PERST# before performing a reboot. The 500ms
is experimentally determined.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown()
export from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2017-08-29 04:43:35 +07:00
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static void iproc_pcie_pltfm_shutdown(struct platform_device *pdev)
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{
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struct iproc_pcie *pcie = platform_get_drvdata(pdev);
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iproc_pcie_shutdown(pcie);
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}
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2015-04-09 01:21:35 +07:00
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static struct platform_driver iproc_pcie_pltfm_driver = {
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.driver = {
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.name = "iproc-pcie",
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.of_match_table = of_match_ptr(iproc_pcie_of_match_table),
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},
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.probe = iproc_pcie_pltfm_probe,
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.remove = iproc_pcie_pltfm_remove,
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PCI: iproc: Add 500ms delay during device shutdown
During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the
LCPLL clock and PERST both go off simultaneously. This seems in accordance
with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the
clock goes inactive after PERST# goes active, but doesn't specify how long
the clock should be valid after PERST#.
However, we have observed that with the iProc Stingray, some Intel NVMe
endpoints, e.g., the P3700 400GB series, are not detected correctly upon
the next boot sequence unless the clock remains valid for some time after
PERST# is asserted.
Delay 500ms after asserting PERST# before performing a reboot. The 500ms
is experimentally determined.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown()
export from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2017-08-29 04:43:35 +07:00
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.shutdown = iproc_pcie_pltfm_shutdown,
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2015-04-09 01:21:35 +07:00
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};
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module_platform_driver(iproc_pcie_pltfm_driver);
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MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iPROC PCIe platform driver");
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MODULE_LICENSE("GPL v2");
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