2016-08-30 20:16:21 +07:00
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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2017-01-03 17:27:13 +07:00
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* This file is distributed in the hope that it will be useful,
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2016-08-30 20:16:21 +07:00
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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2017-01-03 17:27:13 +07:00
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* Or, alternatively,
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2016-08-30 20:16:21 +07:00
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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2017-01-03 17:27:13 +07:00
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* restriction, including without limitation the rights to use,
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2016-08-30 20:16:21 +07:00
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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2017-01-03 17:27:13 +07:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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2016-08-30 20:16:21 +07:00
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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2017-01-03 17:27:13 +07:00
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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2016-08-30 20:16:21 +07:00
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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2017-06-16 14:04:38 +07:00
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#include <dt-bindings/input/input.h>
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#include "imx6ul.dtsi"
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2016-08-30 20:16:21 +07:00
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/ {
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2017-06-16 14:04:39 +07:00
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model = "Engicam GEAM6UL Starter Kit";
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2016-08-30 20:16:21 +07:00
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compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
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2017-06-16 14:04:38 +07:00
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memory {
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reg = <0x80000000 0x08000000>;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm8 0 100000>;
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brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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10 11 12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47 48 49
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50 51 52 53 54 55 56 57 58 59
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60 61 62 63 64 65 66 67 68 69
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70 71 72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87 88 89
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90 91 92 93 94 95 96 97 98 99
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100>;
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default-brightness-level = <100>;
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};
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chosen {
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stdout-path = &uart1;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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2017-06-16 14:04:40 +07:00
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx6ul-geam-sgtl5000";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,widgets =
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"Microphone", "Mic Jack",
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"Line", "Line In",
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"Line", "Line Out",
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"Headphone", "Headphone Jack";
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simple-audio-card,routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&sgtl5000>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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};
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};
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2016-08-30 20:16:21 +07:00
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};
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&can1 {
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2017-06-16 14:04:38 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_3p3v>;
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2016-08-30 20:16:21 +07:00
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status = "okay";
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};
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&can2 {
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2017-06-16 14:04:38 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_3p3v>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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2017-06-16 14:04:40 +07:00
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sgtl5000: codec@a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks IMX6UL_CLK_OSC>;
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clock-names = "mclk";
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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VDDD-supply = <®_1p8v>;
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};
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2017-06-16 14:04:38 +07:00
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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2016-08-30 20:16:21 +07:00
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status = "okay";
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};
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&lcdif {
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2017-06-16 14:04:38 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat
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&pinctrl_lcdif_ctrl>;
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2016-08-30 20:16:21 +07:00
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display = <&display0>;
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status = "okay";
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display0: display {
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bits-per-pixel = <16>;
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bus-width = <18>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <28000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <30>;
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hback-porch = <30>;
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hsync-len = <64>;
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vback-porch = <5>;
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vfront-porch = <5>;
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vsync-len = <20>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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2017-06-16 14:04:38 +07:00
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&pwm8 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm8>;
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status = "okay";
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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status = "okay";
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};
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2016-08-30 20:16:21 +07:00
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&tsc {
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measure-delay-time = <0x1ffff>;
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pre-charge-time = <0x1fff>;
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status = "okay";
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};
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2017-06-16 14:04:38 +07:00
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <4>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
|
|
|
|
MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
|
|
|
|
|
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
|
|
|
|
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_gpmi_nand: gpmi-nand {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
|
|
|
|
|
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
|
|
|
|
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
|
|
|
|
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
|
|
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
|
|
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
|
|
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_lcdif_dat: lcdifdatgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_pwm8: pwm8grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_tsc: tscgrp {
|
|
|
|
|
fsl,pin = <
|
|
|
|
|
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
|
|
|
|
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
|
|
|
|
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
|
|
|
|
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
|
|
|
|
|
MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
|
|
|
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
|
|
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
|
|
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
|
|
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
|
|
|
|
|
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
|
|
|
|
|
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
|
|
|
|
|
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
|
|
|
|
|
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
|
|
|
|
|
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
|
|
|
|
|
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
|
|
|
|
|
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
|
|
|
|
|
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
};
|
