mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
438 lines
11 KiB
C
438 lines
11 KiB
C
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/**
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* encx24j600_hw.h: Register definitions
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*
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*/
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#ifndef _ENCX24J600_HW_H
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#define _ENCX24J600_HW_H
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struct encx24j600_context {
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struct spi_device *spi;
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struct regmap *regmap;
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struct regmap *phymap;
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struct mutex mutex; /* mutex to protect access to regmap */
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int bank;
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};
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void devm_regmap_init_encx24j600(struct device *dev,
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struct encx24j600_context *ctx);
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/* Single-byte instructions */
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#define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))
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#define B0SEL 0xC0 /* Bank 0 Select */
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#define B1SEL 0xC2 /* Bank 1 Select */
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#define B2SEL 0xC4 /* Bank 2 Select */
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#define B3SEL 0xC6 /* Bank 3 Select */
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#define SETETHRST 0xCA /* System Reset */
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#define FCDISABLE 0xE0 /* Flow Control Disable */
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#define FCSINGLE 0xE2 /* Flow Control Single */
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#define FCMULTIPLE 0xE4 /* Flow Control Multiple */
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#define FCCLEAR 0xE6 /* Flow Control Clear */
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#define SETPKTDEC 0xCC /* Decrement Packet Counter */
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#define DMASTOP 0xD2 /* DMA Stop */
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#define DMACKSUM 0xD8 /* DMA Start Checksum */
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#define DMACKSUMS 0xDA /* DMA Start Checksum with Seed */
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#define DMACOPY 0xDC /* DMA Start Copy */
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#define DMACOPYS 0xDE /* DMA Start Copy and Checksum with Seed */
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#define SETTXRTS 0xD4 /* Request Packet Transmission */
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#define ENABLERX 0xE8 /* Enable RX */
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#define DISABLERX 0xEA /* Disable RX */
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#define SETEIE 0xEC /* Enable Interrupts */
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#define CLREIE 0xEE /* Disable Interrupts */
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/* Two byte instructions */
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#define RBSEL 0xC8 /* Read Bank Select */
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/* Three byte instructions */
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#define WGPRDPT 0x60 /* Write EGPRDPT */
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#define RGPRDPT 0x62 /* Read EGPRDPT */
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#define WRXRDPT 0x64 /* Write ERXRDPT */
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#define RRXRDPT 0x66 /* Read ERXRDPT */
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#define WUDARDPT 0x68 /* Write EUDARDPT */
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#define RUDARDPT 0x6A /* Read EUDARDPT */
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#define WGPWRPT 0x6C /* Write EGPWRPT */
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#define RGPWRPT 0x6E /* Read EGPWRPT */
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#define WRXWRPT 0x70 /* Write ERXWRPT */
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#define RRXWRPT 0x72 /* Read ERXWRPT */
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#define WUDAWRPT 0x74 /* Write EUDAWRPT */
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#define RUDAWRPT 0x76 /* Read EUDAWRPT */
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/* n byte instructions */
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#define RCRCODE 0x00
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#define WCRCODE 0x40
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#define BFSCODE 0x80
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#define BFCCODE 0xA0
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#define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
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#define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
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#define RCRU 0x20 /* Read Control Register Unbanked */
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#define WCRU 0x22 /* Write Control Register Unbanked */
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#define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
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#define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
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#define BFSU 0x24 /* Bit Field Set Unbanked */
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#define BFCU 0x26 /* Bit Field Clear Unbanked */
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#define RGPDATA 0x28 /* Read EGPDATA */
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#define WGPDATA 0x2A /* Write EGPDATA */
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#define RRXDATA 0x2C /* Read ERXDATA */
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#define WRXDATA 0x2E /* Write ERXDATA */
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#define RUDADATA 0x30 /* Read EUDADATA */
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#define WUDADATA 0x32 /* Write EUDADATA */
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#define SFR_REG_COUNT 0xA0
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/* ENC424J600 Control Registers
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* Control register definitions are a combination of address
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* and bank number
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* - Register address (bits 0-4)
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* - Bank number (bits 5-6)
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*/
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define BANK_SHIFT 5
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/* All-bank registers */
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#define EUDAST 0x16
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#define EUDAND 0x18
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#define ESTAT 0x1A
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#define EIR 0x1C
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#define ECON1 0x1E
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/* Bank 0 registers */
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#define ETXST (0x00 | 0x00)
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#define ETXLEN (0x02 | 0x00)
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#define ERXST (0x04 | 0x00)
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#define ERXTAIL (0x06 | 0x00)
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#define ERXHEAD (0x08 | 0x00)
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#define EDMAST (0x0A | 0x00)
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#define EDMALEN (0x0C | 0x00)
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#define EDMADST (0x0E | 0x00)
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#define EDMACS (0x10 | 0x00)
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#define ETXSTAT (0x12 | 0x00)
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#define ETXWIRE (0x14 | 0x00)
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/* Bank 1 registers */
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#define EHT1 (0x00 | 0x20)
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#define EHT2 (0x02 | 0x20)
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#define EHT3 (0x04 | 0x20)
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#define EHT4 (0x06 | 0x20)
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#define EPMM1 (0x08 | 0x20)
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#define EPMM2 (0x0A | 0x20)
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#define EPMM3 (0x0C | 0x20)
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#define EPMM4 (0x0E | 0x20)
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#define EPMCS (0x10 | 0x20)
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#define EPMO (0x12 | 0x20)
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#define ERXFCON (0x14 | 0x20)
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/* Bank 2 registers */
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#define MACON1 (0x00 | 0x40)
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#define MACON2 (0x02 | 0x40)
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#define MABBIPG (0x04 | 0x40)
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#define MAIPG (0x06 | 0x40)
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#define MACLCON (0x08 | 0x40)
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#define MAMXFL (0x0A | 0x40)
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#define MICMD (0x12 | 0x40)
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#define MIREGADR (0x14 | 0x40)
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/* Bank 3 registers */
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#define MAADR3 (0x00 | 0x60)
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#define MAADR2 (0x02 | 0x60)
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#define MAADR1 (0x04 | 0x60)
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#define MIWR (0x06 | 0x60)
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#define MIRD (0x08 | 0x60)
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#define MISTAT (0x0A | 0x60)
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#define EPAUS (0x0C | 0x60)
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#define ECON2 (0x0E | 0x60)
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#define ERXWM (0x10 | 0x60)
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#define EIE (0x12 | 0x60)
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#define EIDLED (0x14 | 0x60)
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/* Unbanked registers */
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#define EGPDATA (0x00 | 0x80)
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#define ERXDATA (0x02 | 0x80)
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#define EUDADATA (0x04 | 0x80)
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#define EGPRDPT (0x06 | 0x80)
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#define EGPWRPT (0x08 | 0x80)
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#define ERXRDPT (0x0A | 0x80)
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#define ERXWRPT (0x0C | 0x80)
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#define EUDARDPT (0x0E | 0x80)
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#define EUDAWRPT (0x10 | 0x80)
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/* Register bit definitions */
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/* ESTAT */
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#define INT (1 << 15)
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#define FCIDLE (1 << 14)
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#define RXBUSY (1 << 13)
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#define CLKRDY (1 << 12)
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#define PHYDPX (1 << 10)
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#define PHYLNK (1 << 8)
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/* EIR */
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#define CRYPTEN (1 << 15)
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#define MODEXIF (1 << 14)
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#define HASHIF (1 << 13)
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#define AESIF (1 << 12)
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#define LINKIF (1 << 11)
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#define PKTIF (1 << 6)
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#define DMAIF (1 << 5)
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#define TXIF (1 << 3)
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#define TXABTIF (1 << 2)
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#define RXABTIF (1 << 1)
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#define PCFULIF (1 << 0)
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/* ECON1 */
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#define MODEXST (1 << 15)
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#define HASHEN (1 << 14)
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#define HASHOP (1 << 13)
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#define HASHLST (1 << 12)
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#define AESST (1 << 11)
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#define AESOP1 (1 << 10)
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#define AESOP0 (1 << 9)
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#define PKTDEC (1 << 8)
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#define FCOP1 (1 << 7)
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#define FCOP0 (1 << 6)
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#define DMAST (1 << 5)
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#define DMACPY (1 << 4)
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#define DMACSSD (1 << 3)
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#define DMANOCS (1 << 2)
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#define TXRTS (1 << 1)
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#define RXEN (1 << 0)
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/* ETXSTAT */
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#define LATECOL (1 << 10)
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#define MAXCOL (1 << 9)
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#define EXDEFER (1 << 8)
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#define ETXSTATL_DEFER (1 << 7)
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#define CRCBAD (1 << 4)
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#define COLCNT_MASK 0xF
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/* ERXFCON */
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#define HTEN (1 << 15)
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#define MPEN (1 << 14)
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#define NOTPM (1 << 12)
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#define PMEN3 (1 << 11)
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#define PMEN2 (1 << 10)
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#define PMEN1 (1 << 9)
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#define PMEN0 (1 << 8)
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#define CRCEEN (1 << 7)
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#define CRCEN (1 << 6)
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#define RUNTEEN (1 << 5)
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#define RUNTEN (1 << 4)
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#define UCEN (1 << 3)
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#define NOTMEEN (1 << 2)
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#define MCEN (1 << 1)
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#define BCEN (1 << 0)
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/* MACON1 */
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#define LOOPBK (1 << 4)
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#define RXPAUS (1 << 2)
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#define PASSALL (1 << 1)
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/* MACON2 */
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#define MACON2_DEFER (1 << 14)
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#define BPEN (1 << 13)
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#define NOBKOFF (1 << 12)
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#define PADCFG2 (1 << 7)
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#define PADCFG1 (1 << 6)
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#define PADCFG0 (1 << 5)
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#define TXCRCEN (1 << 4)
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#define PHDREN (1 << 3)
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#define HFRMEN (1 << 2)
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#define MACON2_RSV1 (1 << 1)
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#define FULDPX (1 << 0)
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/* MAIPG */
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/* value of the high byte is given by the reserved bits,
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* value of the low byte is recomended setting of the
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* IPG parameter.
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*/
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#define MAIPGH_VAL 0x0C
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#define MAIPGL_VAL 0x12
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/* MIREGADRH */
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#define MIREGADR_VAL (1 << 8)
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/* MIREGADRL */
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#define PHREG_MASK 0x1F
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/* MICMD */
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#define MIISCAN (1 << 1)
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#define MIIRD (1 << 0)
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/* MISTAT */
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#define NVALID (1 << 2)
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#define SCAN (1 << 1)
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#define BUSY (1 << 0)
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/* ECON2 */
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#define ETHEN (1 << 15)
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#define STRCH (1 << 14)
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#define TXMAC (1 << 13)
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#define SHA1MD5 (1 << 12)
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#define COCON3 (1 << 11)
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#define COCON2 (1 << 10)
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#define COCON1 (1 << 9)
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#define COCON0 (1 << 8)
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#define AUTOFC (1 << 7)
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#define TXRST (1 << 6)
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#define RXRST (1 << 5)
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#define ETHRST (1 << 4)
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#define MODLEN1 (1 << 3)
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#define MODLEN0 (1 << 2)
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#define AESLEN1 (1 << 1)
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#define AESLEN0 (1 << 0)
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/* EIE */
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#define INTIE (1 << 15)
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#define MODEXIE (1 << 14)
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#define HASHIE (1 << 13)
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#define AESIE (1 << 12)
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#define LINKIE (1 << 11)
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#define PKTIE (1 << 6)
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#define DMAIE (1 << 5)
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#define TXIE (1 << 3)
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#define TXABTIE (1 << 2)
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#define RXABTIE (1 << 1)
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#define PCFULIE (1 << 0)
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/* EIDLED */
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#define LACFG3 (1 << 15)
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#define LACFG2 (1 << 14)
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#define LACFG1 (1 << 13)
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#define LACFG0 (1 << 12)
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#define LBCFG3 (1 << 11)
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#define LBCFG2 (1 << 10)
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#define LBCFG1 (1 << 9)
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#define LBCFG0 (1 << 8)
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#define DEVID_SHIFT 5
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#define DEVID_MASK (0x7 << DEVID_SHIFT)
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#define REVID_SHIFT 0
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#define REVID_MASK (0x1F << REVID_SHIFT)
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/* PHY registers */
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHANA 0x04
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#define PHANLPA 0x05
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#define PHANE 0x06
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#define PHCON2 0x11
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#define PHSTAT2 0x1B
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#define PHSTAT3 0x1F
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/* PHCON1 */
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#define PRST (1 << 15)
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#define PLOOPBK (1 << 14)
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#define SPD100 (1 << 13)
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#define ANEN (1 << 12)
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#define PSLEEP (1 << 11)
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#define RENEG (1 << 9)
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#define PFULDPX (1 << 8)
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/* PHSTAT1 */
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#define FULL100 (1 << 14)
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#define HALF100 (1 << 13)
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#define FULL10 (1 << 12)
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#define HALF10 (1 << 11)
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#define ANDONE (1 << 5)
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#define LRFAULT (1 << 4)
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#define ANABLE (1 << 3)
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#define LLSTAT (1 << 2)
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#define EXTREGS (1 << 0)
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/* PHSTAT2 */
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#define PLRITY (1 << 4)
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/* PHSTAT3 */
|
||
|
|
#define PHY3SPD100 (1 << 3)
|
||
|
|
#define PHY3DPX (1 << 4)
|
||
|
|
#define SPDDPX_SHIFT 2
|
||
|
|
#define SPDDPX_MASK (0x7 << SPDDPX_SHIFT)
|
||
|
|
|
||
|
|
/* PHANA */
|
||
|
|
/* Default value for PHY initialization*/
|
||
|
|
#define PHANA_DEFAULT 0x05E1
|
||
|
|
|
||
|
|
/* PHANE */
|
||
|
|
#define PDFLT (1 << 4)
|
||
|
|
#define LPARCD (1 << 1)
|
||
|
|
#define LPANABL (1 << 0)
|
||
|
|
|
||
|
|
#define EUDAST_TEST_VAL 0x1234
|
||
|
|
|
||
|
|
#define TSV_SIZE 7
|
||
|
|
|
||
|
|
#define ENCX24J600_DEV_ID 0x1
|
||
|
|
|
||
|
|
/* Configuration */
|
||
|
|
|
||
|
|
/* Led is on when the link is present and driven low
|
||
|
|
* temporarily when packet is TX'd or RX'd
|
||
|
|
*/
|
||
|
|
#define LED_A_SETTINGS 0xC
|
||
|
|
|
||
|
|
/* Led is on if the link is in 100 Mbps mode */
|
||
|
|
#define LED_B_SETTINGS 0x8
|
||
|
|
|
||
|
|
/* maximum ethernet frame length
|
||
|
|
* Currently not used as a limit anywhere
|
||
|
|
* (we're using the "huge frame enable" feature of
|
||
|
|
* enc424j600).
|
||
|
|
*/
|
||
|
|
#define MAX_FRAMELEN 1518
|
||
|
|
|
||
|
|
/* Size in bytes of the receive buffer in enc424j600.
|
||
|
|
* Must be word aligned (even).
|
||
|
|
*/
|
||
|
|
#define RX_BUFFER_SIZE (15 * MAX_FRAMELEN)
|
||
|
|
|
||
|
|
/* Start of the general purpose area in sram */
|
||
|
|
#define SRAM_GP_START 0x0
|
||
|
|
|
||
|
|
/* SRAM size */
|
||
|
|
#define SRAM_SIZE 0x6000
|
||
|
|
|
||
|
|
/* Start of the receive buffer */
|
||
|
|
#define ERXST_VAL (SRAM_SIZE - RX_BUFFER_SIZE)
|
||
|
|
|
||
|
|
#define RSV_RXLONGEVDROPEV 16
|
||
|
|
#define RSV_CARRIEREV 18
|
||
|
|
#define RSV_CRCERROR 20
|
||
|
|
#define RSV_LENCHECKERR 21
|
||
|
|
#define RSV_LENOUTOFRANGE 22
|
||
|
|
#define RSV_RXOK 23
|
||
|
|
#define RSV_RXMULTICAST 24
|
||
|
|
#define RSV_RXBROADCAST 25
|
||
|
|
#define RSV_DRIBBLENIBBLE 26
|
||
|
|
#define RSV_RXCONTROLFRAME 27
|
||
|
|
#define RSV_RXPAUSEFRAME 28
|
||
|
|
#define RSV_RXUNKNOWNOPCODE 29
|
||
|
|
#define RSV_RXTYPEVLAN 30
|
||
|
|
|
||
|
|
#define RSV_RUNTFILTERMATCH 31
|
||
|
|
#define RSV_NOTMEFILTERMATCH 32
|
||
|
|
#define RSV_HASHFILTERMATCH 33
|
||
|
|
#define RSV_MAGICPKTFILTERMATCH 34
|
||
|
|
#define RSV_PTRNMTCHFILTERMATCH 35
|
||
|
|
#define RSV_UNICASTFILTERMATCH 36
|
||
|
|
|
||
|
|
#define RSV_SIZE 8
|
||
|
|
#define RSV_BITMASK(x) (1 << ((x) - 16))
|
||
|
|
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
|
||
|
|
|
||
|
|
struct rsv {
|
||
|
|
u16 next_packet;
|
||
|
|
u16 len;
|
||
|
|
u32 rxstat;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Put RX buffer at 0 as suggested by the Errata datasheet */
|
||
|
|
|
||
|
|
#define RXSTART_INIT ERXST_VAL
|
||
|
|
#define RXEND_INIT 0x5FFF
|
||
|
|
|
||
|
|
int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
|
||
|
|
size_t count);
|
||
|
|
int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count);
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|