2005-04-17 05:20:36 +07:00
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/*
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* (C) Copyright 2003-2004
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* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
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* This is a combined i2c adapter and algorithm driver for the
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* MPC107/Tsi107 PowerPC northbridge and processors that include
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* the same I2C unit (8240, 8245, 85xx).
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*
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* Release 0.8
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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2017-02-03 01:15:33 +07:00
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#include <linux/sched/signal.h>
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2013-09-18 02:28:33 +07:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2008-07-01 06:01:26 +07:00
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#include <linux/of_platform.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2005-10-30 01:07:23 +07:00
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2013-08-23 23:01:44 +07:00
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#include <linux/clk.h>
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2009-04-07 15:20:53 +07:00
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#include <linux/io.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/fsl_devices.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
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#include <asm/mpc52xx.h>
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2015-02-10 22:46:33 +07:00
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#include <asm/mpc85xx.h>
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i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
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#include <sysdev/fsl_soc.h>
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2008-07-01 06:01:26 +07:00
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#define DRV_NAME "mpc-i2c"
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2010-02-17 17:19:19 +07:00
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#define MPC_I2C_CLOCK_LEGACY 0
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#define MPC_I2C_CLOCK_PRESERVE (~0U)
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2009-04-07 15:20:53 +07:00
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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#define MPC_I2C_DR 0x10
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2005-04-17 05:20:36 +07:00
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#define MPC_I2C_DFSRR 0x14
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#define CCR_MEN 0x80
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#define CCR_MIEN 0x40
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#define CCR_MSTA 0x20
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#define CCR_MTX 0x10
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#define CCR_TXAK 0x08
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#define CCR_RSTA 0x04
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#define CSR_MCF 0x80
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#define CSR_MAAS 0x40
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#define CSR_MBB 0x20
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#define CSR_MAL 0x10
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#define CSR_SRW 0x04
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#define CSR_MIF 0x02
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#define CSR_RXAK 0x01
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struct mpc_i2c {
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2009-04-07 15:20:54 +07:00
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struct device *dev;
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2005-04-26 08:32:12 +07:00
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void __iomem *base;
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2005-04-17 05:20:36 +07:00
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u32 interrupt;
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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2010-02-17 15:59:14 +07:00
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u32 real_clk;
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2013-07-15 09:28:23 +07:00
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#ifdef CONFIG_PM_SLEEP
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2012-04-19 16:51:34 +07:00
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u8 fdr, dfsrr;
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#endif
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2013-08-23 23:01:44 +07:00
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struct clk *clk_per;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
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};
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struct mpc_i2c_divider {
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u16 divider;
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u16 fdr; /* including dfsrr */
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};
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2010-02-17 17:19:17 +07:00
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struct mpc_i2c_data {
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2018-01-10 18:36:07 +07:00
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void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
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2005-04-17 05:20:36 +07:00
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};
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2009-04-07 15:20:53 +07:00
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static inline void writeccr(struct mpc_i2c *i2c, u32 x)
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2005-04-17 05:20:36 +07:00
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{
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writeb(x, i2c->base + MPC_I2C_CR);
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}
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 20:55:46 +07:00
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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2005-04-17 05:20:36 +07:00
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{
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struct mpc_i2c *i2c = dev_id;
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if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
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/* Read again to allow register to stabilise */
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i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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2009-02-06 21:00:37 +07:00
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wake_up(&i2c->queue);
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2015-03-27 19:49:00 +07:00
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return IRQ_HANDLED;
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2005-04-17 05:20:36 +07:00
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}
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2015-03-27 19:49:00 +07:00
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return IRQ_NONE;
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2005-04-17 05:20:36 +07:00
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}
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2007-07-12 19:12:31 +07:00
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/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
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* the bus, because it wants to send ACK.
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* Following sequence of enabling/disabling and sending start/stop generates
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2010-02-17 15:59:14 +07:00
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* the 9 pulses, so it's all OK.
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2007-07-12 19:12:31 +07:00
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*/
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static void mpc_i2c_fixup(struct mpc_i2c *i2c)
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{
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2010-02-17 15:59:14 +07:00
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int k;
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u32 delay_val = 1000000 / i2c->real_clk + 1;
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if (delay_val < 2)
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delay_val = 2;
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for (k = 9; k; k--) {
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writeccr(i2c, 0);
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writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
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2014-06-03 16:00:32 +07:00
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readb(i2c->base + MPC_I2C_DR);
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2010-02-17 15:59:14 +07:00
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writeccr(i2c, CCR_MEN);
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udelay(delay_val << 1);
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}
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2007-07-12 19:12:31 +07:00
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}
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2005-04-17 05:20:36 +07:00
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static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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{
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unsigned long orig_jiffies = jiffies;
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2014-11-12 20:08:09 +07:00
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u32 cmd_err;
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2005-04-17 05:20:36 +07:00
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int result = 0;
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2009-10-04 18:08:16 +07:00
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if (!i2c->irq) {
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2005-04-17 05:20:36 +07:00
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while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
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schedule();
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if (time_after(jiffies, orig_jiffies + timeout)) {
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2009-04-07 15:20:54 +07:00
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dev_dbg(i2c->dev, "timeout\n");
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2007-08-14 23:37:14 +07:00
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writeccr(i2c, 0);
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2014-11-12 20:08:09 +07:00
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result = -ETIMEDOUT;
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2005-04-17 05:20:36 +07:00
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break;
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}
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}
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2014-11-12 20:08:09 +07:00
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cmd_err = readb(i2c->base + MPC_I2C_SR);
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2005-04-17 05:20:36 +07:00
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writeb(0, i2c->base + MPC_I2C_SR);
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} else {
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/* Interrupt mode */
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2009-02-06 21:00:37 +07:00
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result = wait_event_timeout(i2c->queue,
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2009-03-29 03:34:43 +07:00
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(i2c->interrupt & CSR_MIF), timeout);
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2005-04-17 05:20:36 +07:00
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2009-02-06 21:00:37 +07:00
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if (unlikely(!(i2c->interrupt & CSR_MIF))) {
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2009-04-07 15:20:54 +07:00
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dev_dbg(i2c->dev, "wait timeout\n");
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2007-08-14 23:37:14 +07:00
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writeccr(i2c, 0);
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2005-04-17 05:20:36 +07:00
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result = -ETIMEDOUT;
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}
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2014-11-12 20:08:09 +07:00
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cmd_err = i2c->interrupt;
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2005-04-17 05:20:36 +07:00
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i2c->interrupt = 0;
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}
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if (result < 0)
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return result;
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2014-11-12 20:08:09 +07:00
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if (!(cmd_err & CSR_MCF)) {
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2009-04-07 15:20:54 +07:00
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dev_dbg(i2c->dev, "unfinished\n");
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2005-04-17 05:20:36 +07:00
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return -EIO;
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}
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2014-11-12 20:08:09 +07:00
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if (cmd_err & CSR_MAL) {
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2009-04-07 15:20:54 +07:00
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dev_dbg(i2c->dev, "MAL\n");
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2014-11-12 20:08:09 +07:00
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return -EAGAIN;
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2005-04-17 05:20:36 +07:00
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}
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2014-11-12 20:08:09 +07:00
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if (writing && (cmd_err & CSR_RXAK)) {
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_dbg(i2c->dev, "No RXAK\n");
|
2005-04-17 05:20:36 +07:00
|
|
|
/* generate stop */
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
2014-11-12 20:08:09 +07:00
|
|
|
return -ENXIO;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-17 17:19:19 +07:00
|
|
|
#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
|
|
|
|
|
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
|
|
|
|
|
{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
|
|
|
|
|
{52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
|
|
|
|
|
{68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
|
|
|
|
|
{96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
|
|
|
|
|
{128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
|
|
|
|
|
{176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
|
|
|
|
|
{240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
|
|
|
|
|
{320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
|
|
|
|
|
{448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
|
|
|
|
|
{640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
|
|
|
|
|
{1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
|
|
|
|
|
{1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
|
|
|
|
|
{2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
|
|
|
|
|
{4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
|
|
|
|
|
{7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
|
|
|
|
|
{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 *real_clk)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
2009-04-09 16:59:52 +07:00
|
|
|
const struct mpc_i2c_divider *div = NULL;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
unsigned int pvr = mfspr(SPRN_PVR);
|
|
|
|
|
u32 divider;
|
|
|
|
|
int i;
|
|
|
|
|
|
2010-02-17 15:59:14 +07:00
|
|
|
if (clock == MPC_I2C_CLOCK_LEGACY) {
|
|
|
|
|
/* see below - default fdr = 0x3f -> div = 2048 */
|
|
|
|
|
*real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
return -EINVAL;
|
2010-02-17 15:59:14 +07:00
|
|
|
}
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
/* Determine divider value */
|
2009-06-17 13:30:22 +07:00
|
|
|
divider = mpc5xxx_get_bus_frequency(node) / clock;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We want to choose an FDR/DFSR that generates an I2C bus speed that
|
|
|
|
|
* is equal to or lower than the requested speed.
|
|
|
|
|
*/
|
2009-04-09 16:59:52 +07:00
|
|
|
for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
div = &mpc_i2c_dividers_52xx[i];
|
|
|
|
|
/* Old MPC5200 rev A CPUs do not support the high bits */
|
|
|
|
|
if (div->fdr & 0xc0 && pvr == 0x80822011)
|
|
|
|
|
continue;
|
|
|
|
|
if (div->divider >= divider)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-17 15:59:14 +07:00
|
|
|
*real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
|
|
|
|
|
return (int)div->fdr;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
}
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_52xx(struct device_node *node,
|
2010-02-17 17:19:18 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
2009-04-09 16:59:52 +07:00
|
|
|
int ret, fdr;
|
|
|
|
|
|
2010-02-17 17:19:19 +07:00
|
|
|
if (clock == MPC_I2C_CLOCK_PRESERVE) {
|
|
|
|
|
dev_dbg(i2c->dev, "using fdr %d\n",
|
|
|
|
|
readb(i2c->base + MPC_I2C_FDR));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-10 18:36:07 +07:00
|
|
|
ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
|
2009-04-09 16:59:52 +07:00
|
|
|
fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
|
2009-04-09 16:59:52 +07:00
|
|
|
|
|
|
|
|
if (ret >= 0)
|
2010-02-17 15:59:14 +07:00
|
|
|
dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
|
|
|
|
|
fdr);
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
}
|
2010-02-17 17:19:19 +07:00
|
|
|
#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_52xx(struct device_node *node,
|
2010-02-17 17:19:18 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
|
|
|
|
}
|
2010-02-17 17:19:19 +07:00
|
|
|
#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_MPC512x
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_512x(struct device_node *node,
|
2010-02-17 17:19:19 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
2010-02-17 17:19:19 +07:00
|
|
|
{
|
|
|
|
|
struct device_node *node_ctrl;
|
|
|
|
|
void __iomem *ctrl;
|
|
|
|
|
const u32 *pval;
|
|
|
|
|
u32 idx;
|
|
|
|
|
|
|
|
|
|
/* Enable I2C interrupts for mpc5121 */
|
|
|
|
|
node_ctrl = of_find_compatible_node(NULL, NULL,
|
|
|
|
|
"fsl,mpc5121-i2c-ctrl");
|
|
|
|
|
if (node_ctrl) {
|
|
|
|
|
ctrl = of_iomap(node_ctrl, 0);
|
|
|
|
|
if (ctrl) {
|
|
|
|
|
/* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
|
|
|
|
|
pval = of_get_property(node, "reg", NULL);
|
|
|
|
|
idx = (*pval & 0xff) / 0x20;
|
|
|
|
|
setbits32(ctrl, 1 << (24 + idx * 2));
|
|
|
|
|
iounmap(ctrl);
|
|
|
|
|
}
|
|
|
|
|
of_node_put(node_ctrl);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* The clock setup for the 52xx works also fine for the 512x */
|
2018-01-10 18:36:07 +07:00
|
|
|
mpc_i2c_setup_52xx(node, i2c, clock);
|
2010-02-17 17:19:19 +07:00
|
|
|
}
|
|
|
|
|
#else /* CONFIG_PPC_MPC512x */
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_512x(struct device_node *node,
|
2010-02-17 17:19:19 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
2010-02-17 17:19:19 +07:00
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC_MPC512x */
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_SOC
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
|
|
|
|
|
{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
|
|
|
|
|
{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
|
|
|
|
|
{544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
|
|
|
|
|
{672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
|
|
|
|
|
{800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
|
|
|
|
|
{1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
|
|
|
|
|
{1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
|
|
|
|
|
{1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
|
|
|
|
|
{2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
|
|
|
|
|
{3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
|
|
|
|
|
{4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
|
|
|
|
|
{7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
|
|
|
|
|
{12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
|
|
|
|
|
{18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
|
|
|
|
|
{30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
|
|
|
|
|
{49152, 0x011e}, {61440, 0x011f}
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static u32 mpc_i2c_get_sec_cfg_8xxx(void)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
2017-10-28 03:24:44 +07:00
|
|
|
struct device_node *node;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
u32 __iomem *reg;
|
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
|
|
node = of_find_node_by_name(NULL, "global-utilities");
|
|
|
|
|
if (node) {
|
|
|
|
|
const u32 *prop = of_get_property(node, "reg", NULL);
|
|
|
|
|
if (prop) {
|
|
|
|
|
/*
|
|
|
|
|
* Map and check POR Device Status Register 2
|
2017-12-07 17:20:02 +07:00
|
|
|
* (PORDEVSR2) at 0xE0014. Note than while MPC8533
|
|
|
|
|
* and MPC8544 indicate SEC frequency ratio
|
|
|
|
|
* configuration as bit 26 in PORDEVSR2, other MPC8xxx
|
|
|
|
|
* parts may store it differently or may not have it
|
|
|
|
|
* at all.
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
*/
|
|
|
|
|
reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
|
|
|
|
|
if (!reg)
|
|
|
|
|
printk(KERN_ERR
|
|
|
|
|
"Error: couldn't map PORDEVSR2\n");
|
|
|
|
|
else
|
2017-12-07 17:20:02 +07:00
|
|
|
val = in_be32(reg) & 0x00000020; /* sec-cfg */
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
iounmap(reg);
|
|
|
|
|
}
|
|
|
|
|
}
|
2014-08-08 17:07:42 +07:00
|
|
|
of_node_put(node);
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-10 22:46:33 +07:00
|
|
|
static u32 mpc_i2c_get_prescaler_8xxx(void)
|
|
|
|
|
{
|
2017-12-07 17:20:01 +07:00
|
|
|
/*
|
|
|
|
|
* According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
|
|
|
|
|
* may have prescaler 1, 2, or 3, depending on the power-on
|
|
|
|
|
* configuration.
|
|
|
|
|
*/
|
2015-02-10 22:46:33 +07:00
|
|
|
u32 prescaler = 1;
|
|
|
|
|
|
|
|
|
|
/* mpc85xx */
|
|
|
|
|
if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
|
|
|
|
|
|| pvr_version_is(PVR_VER_E500MC)
|
|
|
|
|
|| pvr_version_is(PVR_VER_E5500)
|
|
|
|
|
|| pvr_version_is(PVR_VER_E6500)) {
|
|
|
|
|
unsigned int svr = mfspr(SPRN_SVR);
|
|
|
|
|
|
|
|
|
|
if ((SVR_SOC_VER(svr) == SVR_8540)
|
|
|
|
|
|| (SVR_SOC_VER(svr) == SVR_8541)
|
|
|
|
|
|| (SVR_SOC_VER(svr) == SVR_8560)
|
|
|
|
|
|| (SVR_SOC_VER(svr) == SVR_8555)
|
|
|
|
|
|| (SVR_SOC_VER(svr) == SVR_8610))
|
|
|
|
|
/* the above 85xx SoCs have prescaler 1 */
|
|
|
|
|
prescaler = 1;
|
2017-12-07 17:20:01 +07:00
|
|
|
else if ((SVR_SOC_VER(svr) == SVR_8533)
|
|
|
|
|
|| (SVR_SOC_VER(svr) == SVR_8544))
|
|
|
|
|
/* the above 85xx SoCs have prescaler 3 or 2 */
|
|
|
|
|
prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
|
2015-02-10 22:46:33 +07:00
|
|
|
else
|
|
|
|
|
/* all the other 85xx have prescaler 2 */
|
|
|
|
|
prescaler = 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return prescaler;
|
|
|
|
|
}
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 *real_clk)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
|
|
|
|
const struct mpc_i2c_divider *div = NULL;
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 prescaler = mpc_i2c_get_prescaler_8xxx();
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
u32 divider;
|
|
|
|
|
int i;
|
|
|
|
|
|
2017-12-07 17:20:00 +07:00
|
|
|
if (clock == MPC_I2C_CLOCK_LEGACY) {
|
|
|
|
|
/* see below - default fdr = 0x1031 -> div = 16 * 3072 */
|
|
|
|
|
*real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
divider = fsl_get_sys_freq() / clock / prescaler;
|
|
|
|
|
|
|
|
|
|
pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
|
|
|
|
|
fsl_get_sys_freq(), clock, divider);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We want to choose an FDR/DFSR that generates an I2C bus speed that
|
|
|
|
|
* is equal to or lower than the requested speed.
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
|
|
|
|
|
div = &mpc_i2c_dividers_8xxx[i];
|
|
|
|
|
if (div->divider >= divider)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-17 15:59:14 +07:00
|
|
|
*real_clk = fsl_get_sys_freq() / prescaler / div->divider;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
return div ? (int)div->fdr : -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_8xxx(struct device_node *node,
|
2010-02-17 17:19:18 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
{
|
2009-04-09 16:59:52 +07:00
|
|
|
int ret, fdr;
|
|
|
|
|
|
2010-02-17 17:19:19 +07:00
|
|
|
if (clock == MPC_I2C_CLOCK_PRESERVE) {
|
|
|
|
|
dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
|
|
|
|
|
readb(i2c->base + MPC_I2C_DFSRR),
|
|
|
|
|
readb(i2c->base + MPC_I2C_FDR));
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-10 18:36:07 +07:00
|
|
|
ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
|
2009-04-09 16:59:52 +07:00
|
|
|
fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
|
|
|
|
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
|
|
|
|
|
writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
|
2009-04-09 16:59:52 +07:00
|
|
|
|
|
|
|
|
if (ret >= 0)
|
|
|
|
|
dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
|
2010-02-17 15:59:14 +07:00
|
|
|
i2c->real_clk, fdr >> 8, fdr & 0xff);
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else /* !CONFIG_FSL_SOC */
|
2012-11-28 03:59:38 +07:00
|
|
|
static void mpc_i2c_setup_8xxx(struct device_node *node,
|
2010-02-17 17:19:18 +07:00
|
|
|
struct mpc_i2c *i2c,
|
2018-01-10 18:36:07 +07:00
|
|
|
u32 clock)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
|
}
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
#endif /* CONFIG_FSL_SOC */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
static void mpc_i2c_start(struct mpc_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
/* Clear arbitration */
|
|
|
|
|
writeb(0, i2c->base + MPC_I2C_SR);
|
|
|
|
|
/* Start with MEN */
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mpc_i2c_stop(struct mpc_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_write(struct mpc_i2c *i2c, int target,
|
2009-04-07 15:20:53 +07:00
|
|
|
const u8 *data, int length, int restart)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2008-01-28 00:14:52 +07:00
|
|
|
int i, result;
|
2005-04-17 05:20:36 +07:00
|
|
|
unsigned timeout = i2c->adap.timeout;
|
|
|
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
|
|
|
|
|
|
/* Start as master */
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
|
|
|
/* Write target byte */
|
|
|
|
|
writeb((target << 1), i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-28 00:14:52 +07:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
|
|
|
|
/* Write data byte */
|
|
|
|
|
writeb(data[i], i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-28 00:14:52 +07:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_read(struct mpc_i2c *i2c, int target,
|
2012-02-23 16:42:45 +07:00
|
|
|
u8 *data, int length, int restart, bool recv_len)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
|
unsigned timeout = i2c->adap.timeout;
|
2008-01-28 00:14:52 +07:00
|
|
|
int i, result;
|
2005-04-17 05:20:36 +07:00
|
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
|
|
|
|
|
|
/* Switch to read - restart */
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
|
|
|
/* Write target address byte - this time with the read flag set */
|
|
|
|
|
writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-28 00:14:52 +07:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
if (length) {
|
2012-02-23 16:42:45 +07:00
|
|
|
if (length == 1 && !recv_len)
|
2005-04-17 05:20:36 +07:00
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
|
|
|
|
|
else
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
|
|
|
|
|
/* Dummy read */
|
|
|
|
|
readb(i2c->base + MPC_I2C_DR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
2012-02-23 16:42:45 +07:00
|
|
|
u8 byte;
|
|
|
|
|
|
2008-01-28 00:14:52 +07:00
|
|
|
result = i2c_wait(i2c, timeout, 0);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-02-23 16:42:45 +07:00
|
|
|
/*
|
|
|
|
|
* For block reads, we have to know the total length (1st byte)
|
|
|
|
|
* before we can determine if we are done.
|
|
|
|
|
*/
|
|
|
|
|
if (i || !recv_len) {
|
|
|
|
|
/* Generate txack on next to last byte */
|
|
|
|
|
if (i == length - 2)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
|
|
|
| CCR_TXAK);
|
|
|
|
|
/* Do not generate stop on last byte */
|
|
|
|
|
if (i == length - 1)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
|
|
|
| CCR_MTX);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte = readb(i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Adjust length if first received byte is length.
|
|
|
|
|
* The length is 1 length byte plus actually data length
|
|
|
|
|
*/
|
|
|
|
|
if (i == 0 && recv_len) {
|
|
|
|
|
if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
|
|
|
|
|
return -EPROTO;
|
|
|
|
|
length += byte;
|
|
|
|
|
/*
|
|
|
|
|
* For block reads, generate txack here if data length
|
|
|
|
|
* is 1 byte (total length is 2 bytes).
|
|
|
|
|
*/
|
|
|
|
|
if (length == 2)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
|
|
|
|
|
| CCR_TXAK);
|
|
|
|
|
}
|
|
|
|
|
data[i] = byte;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return length;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
|
|
|
{
|
|
|
|
|
struct i2c_msg *pmsg;
|
|
|
|
|
int i;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
unsigned long orig_jiffies = jiffies;
|
|
|
|
|
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
|
|
mpc_i2c_start(i2c);
|
|
|
|
|
|
|
|
|
|
/* Allow bus up to 1s to become not busy */
|
|
|
|
|
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
|
|
|
|
if (signal_pending(current)) {
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_dbg(i2c->dev, "Interrupted\n");
|
2007-08-14 23:37:14 +07:00
|
|
|
writeccr(i2c, 0);
|
2005-04-17 05:20:36 +07:00
|
|
|
return -EINTR;
|
|
|
|
|
}
|
|
|
|
|
if (time_after(jiffies, orig_jiffies + HZ)) {
|
2010-02-17 15:59:14 +07:00
|
|
|
u8 status = readb(i2c->base + MPC_I2C_SR);
|
|
|
|
|
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_dbg(i2c->dev, "timeout\n");
|
2010-02-17 15:59:14 +07:00
|
|
|
if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
|
|
|
|
|
writeb(status & ~CSR_MAL,
|
|
|
|
|
i2c->base + MPC_I2C_SR);
|
2007-07-12 19:12:31 +07:00
|
|
|
mpc_i2c_fixup(i2c);
|
2010-02-17 15:59:14 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
schedule();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; ret >= 0 && i < num; i++) {
|
|
|
|
|
pmsg = &msgs[i];
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_dbg(i2c->dev,
|
|
|
|
|
"Doing %s %d bytes to 0x%02x - %d of %d messages\n",
|
|
|
|
|
pmsg->flags & I2C_M_RD ? "read" : "write",
|
|
|
|
|
pmsg->len, pmsg->addr, i + 1, num);
|
2012-02-23 16:42:45 +07:00
|
|
|
if (pmsg->flags & I2C_M_RD) {
|
|
|
|
|
bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
|
|
|
|
|
|
|
|
|
|
ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
|
|
|
|
|
recv_len);
|
|
|
|
|
if (recv_len && ret > 0)
|
|
|
|
|
pmsg->len = ret;
|
|
|
|
|
} else {
|
2005-04-17 05:20:36 +07:00
|
|
|
ret =
|
|
|
|
|
mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
|
2012-02-23 16:42:45 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2012-08-30 17:40:04 +07:00
|
|
|
mpc_i2c_stop(i2c); /* Initiate STOP */
|
|
|
|
|
orig_jiffies = jiffies;
|
|
|
|
|
/* Wait until STOP is seen, allow up to 1 s */
|
|
|
|
|
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
|
|
|
|
if (time_after(jiffies, orig_jiffies + HZ)) {
|
|
|
|
|
u8 status = readb(i2c->base + MPC_I2C_SR);
|
|
|
|
|
|
|
|
|
|
dev_dbg(i2c->dev, "timeout\n");
|
|
|
|
|
if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
|
|
|
|
|
writeb(status & ~CSR_MAL,
|
|
|
|
|
i2c->base + MPC_I2C_SR);
|
|
|
|
|
mpc_i2c_fixup(i2c);
|
|
|
|
|
}
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
cond_resched();
|
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
return (ret < 0) ? ret : num;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 mpc_functionality(struct i2c_adapter *adap)
|
|
|
|
|
{
|
2012-02-23 16:42:45 +07:00
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
|
|
|
|
|
| I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2006-09-04 03:39:46 +07:00
|
|
|
static const struct i2c_algorithm mpc_algo = {
|
2005-04-17 05:20:36 +07:00
|
|
|
.master_xfer = mpc_xfer,
|
|
|
|
|
.functionality = mpc_functionality,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct i2c_adapter mpc_ops = {
|
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.algo = &mpc_algo,
|
2009-03-29 03:34:43 +07:00
|
|
|
.timeout = HZ,
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
2011-05-19 00:19:24 +07:00
|
|
|
static const struct of_device_id mpc_i2c_of_match[];
|
2012-11-28 03:59:38 +07:00
|
|
|
static int fsl_i2c_probe(struct platform_device *op)
|
2005-07-28 01:43:26 +07:00
|
|
|
{
|
2011-05-19 00:19:24 +07:00
|
|
|
const struct of_device_id *match;
|
2005-07-28 01:43:26 +07:00
|
|
|
struct mpc_i2c *i2c;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
const u32 *prop;
|
2010-02-17 17:19:19 +07:00
|
|
|
u32 clock = MPC_I2C_CLOCK_LEGACY;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
int result = 0;
|
|
|
|
|
int plen;
|
2013-07-11 02:03:21 +07:00
|
|
|
struct resource res;
|
2013-08-23 23:01:44 +07:00
|
|
|
struct clk *clk;
|
|
|
|
|
int err;
|
2005-07-28 01:43:26 +07:00
|
|
|
|
2011-05-19 00:19:24 +07:00
|
|
|
match = of_match_device(mpc_i2c_of_match, &op->dev);
|
|
|
|
|
if (!match)
|
2011-02-17 16:43:24 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
2008-01-28 00:14:52 +07:00
|
|
|
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
|
|
|
|
|
if (!i2c)
|
2005-07-28 01:43:26 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2009-04-07 15:20:54 +07:00
|
|
|
i2c->dev = &op->dev; /* for debug and error output */
|
|
|
|
|
|
2008-07-01 06:01:26 +07:00
|
|
|
init_waitqueue_head(&i2c->queue);
|
2005-07-28 01:43:26 +07:00
|
|
|
|
2010-04-14 06:12:29 +07:00
|
|
|
i2c->base = of_iomap(op->dev.of_node, 0);
|
2005-07-28 01:43:26 +07:00
|
|
|
if (!i2c->base) {
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_err(i2c->dev, "failed to map controller\n");
|
2005-07-28 01:43:26 +07:00
|
|
|
result = -ENOMEM;
|
|
|
|
|
goto fail_map;
|
|
|
|
|
}
|
|
|
|
|
|
2010-04-14 06:12:29 +07:00
|
|
|
i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
|
2009-10-04 18:08:16 +07:00
|
|
|
if (i2c->irq) { /* no i2c->irq implies polling */
|
2008-07-01 06:01:26 +07:00
|
|
|
result = request_irq(i2c->irq, mpc_i2c_isr,
|
|
|
|
|
IRQF_SHARED, "i2c-mpc", i2c);
|
|
|
|
|
if (result < 0) {
|
2009-04-07 15:20:54 +07:00
|
|
|
dev_err(i2c->dev, "failed to attach interrupt\n");
|
2008-07-01 06:01:26 +07:00
|
|
|
goto fail_request;
|
2005-07-28 01:43:26 +07:00
|
|
|
}
|
2008-07-01 06:01:26 +07:00
|
|
|
}
|
2009-04-07 15:20:53 +07:00
|
|
|
|
2013-08-23 23:01:44 +07:00
|
|
|
/*
|
|
|
|
|
* enable clock for the I2C peripheral (non fatal),
|
|
|
|
|
* keep a reference upon successful allocation
|
|
|
|
|
*/
|
|
|
|
|
clk = devm_clk_get(&op->dev, NULL);
|
|
|
|
|
if (!IS_ERR(clk)) {
|
|
|
|
|
err = clk_prepare_enable(clk);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&op->dev, "failed to enable clock\n");
|
|
|
|
|
goto fail_request;
|
|
|
|
|
} else {
|
|
|
|
|
i2c->clk_per = clk;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-05 15:56:44 +07:00
|
|
|
if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
|
2010-02-17 17:19:19 +07:00
|
|
|
clock = MPC_I2C_CLOCK_PRESERVE;
|
|
|
|
|
} else {
|
2010-04-14 06:12:29 +07:00
|
|
|
prop = of_get_property(op->dev.of_node, "clock-frequency",
|
|
|
|
|
&plen);
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
if (prop && plen == sizeof(u32))
|
|
|
|
|
clock = *prop;
|
2010-02-17 17:19:19 +07:00
|
|
|
}
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
|
2011-05-19 00:19:24 +07:00
|
|
|
if (match->data) {
|
2012-05-22 02:57:39 +07:00
|
|
|
const struct mpc_i2c_data *data = match->data;
|
2018-01-10 18:36:07 +07:00
|
|
|
data->setup(op->dev.of_node, i2c, clock);
|
2010-02-17 17:19:19 +07:00
|
|
|
} else {
|
|
|
|
|
/* Backwards compatibility */
|
2010-04-14 06:12:29 +07:00
|
|
|
if (of_get_property(op->dev.of_node, "dfsrr", NULL))
|
2018-01-10 18:36:07 +07:00
|
|
|
mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
}
|
2008-07-01 06:01:26 +07:00
|
|
|
|
2010-02-17 15:59:14 +07:00
|
|
|
prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
|
|
|
|
|
if (prop && plen == sizeof(u32)) {
|
|
|
|
|
mpc_ops.timeout = *prop * HZ / 1000000;
|
|
|
|
|
if (mpc_ops.timeout < 5)
|
|
|
|
|
mpc_ops.timeout = 5;
|
|
|
|
|
}
|
|
|
|
|
dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
|
|
|
|
|
|
2013-05-23 17:22:40 +07:00
|
|
|
platform_set_drvdata(op, i2c);
|
2005-07-28 01:43:26 +07:00
|
|
|
|
|
|
|
|
i2c->adap = mpc_ops;
|
2013-07-11 02:03:21 +07:00
|
|
|
of_address_to_resource(op->dev.of_node, 0, &res);
|
|
|
|
|
scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
|
|
|
|
|
"MPC adapter at 0x%llx", (unsigned long long)res.start);
|
2005-07-28 01:43:26 +07:00
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
2008-07-01 06:01:26 +07:00
|
|
|
i2c->adap.dev.parent = &op->dev;
|
2010-06-08 20:48:18 +07:00
|
|
|
i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
|
2008-07-01 06:01:26 +07:00
|
|
|
|
|
|
|
|
result = i2c_add_adapter(&i2c->adap);
|
2016-08-09 18:36:17 +07:00
|
|
|
if (result < 0)
|
2005-07-28 01:43:26 +07:00
|
|
|
goto fail_add;
|
|
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
|
2008-07-01 06:01:26 +07:00
|
|
|
fail_add:
|
2013-08-23 23:01:44 +07:00
|
|
|
if (i2c->clk_per)
|
|
|
|
|
clk_disable_unprepare(i2c->clk_per);
|
2008-07-01 06:01:26 +07:00
|
|
|
free_irq(i2c->irq, i2c);
|
|
|
|
|
fail_request:
|
|
|
|
|
irq_dispose_mapping(i2c->irq);
|
2009-04-07 15:20:53 +07:00
|
|
|
iounmap(i2c->base);
|
2008-07-01 06:01:26 +07:00
|
|
|
fail_map:
|
2005-07-28 01:43:26 +07:00
|
|
|
kfree(i2c);
|
|
|
|
|
return result;
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static int fsl_i2c_remove(struct platform_device *op)
|
2005-07-28 01:43:26 +07:00
|
|
|
{
|
2013-05-23 17:22:40 +07:00
|
|
|
struct mpc_i2c *i2c = platform_get_drvdata(op);
|
2005-07-28 01:43:26 +07:00
|
|
|
|
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
|
|
2013-08-23 23:01:44 +07:00
|
|
|
if (i2c->clk_per)
|
|
|
|
|
clk_disable_unprepare(i2c->clk_per);
|
|
|
|
|
|
2009-10-04 18:08:16 +07:00
|
|
|
if (i2c->irq)
|
2005-07-28 01:43:26 +07:00
|
|
|
free_irq(i2c->irq, i2c);
|
|
|
|
|
|
2008-07-01 06:01:26 +07:00
|
|
|
irq_dispose_mapping(i2c->irq);
|
2005-07-28 01:43:26 +07:00
|
|
|
iounmap(i2c->base);
|
|
|
|
|
kfree(i2c);
|
|
|
|
|
return 0;
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-15 09:28:23 +07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2012-04-19 16:51:34 +07:00
|
|
|
static int mpc_i2c_suspend(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mpc_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
|
|
|
|
|
i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_i2c_resume(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct mpc_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
|
|
|
|
|
writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-15 09:28:23 +07:00
|
|
|
static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
|
|
|
|
|
#define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
|
|
|
|
|
#else
|
|
|
|
|
#define MPC_I2C_PM_OPS NULL
|
2012-04-19 16:51:34 +07:00
|
|
|
#endif
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_512x = {
|
2010-02-17 17:19:19 +07:00
|
|
|
.setup = mpc_i2c_setup_512x,
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_52xx = {
|
2010-02-17 17:19:18 +07:00
|
|
|
.setup = mpc_i2c_setup_52xx,
|
2010-02-17 17:19:17 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8313 = {
|
2010-02-17 17:19:18 +07:00
|
|
|
.setup = mpc_i2c_setup_8xxx,
|
2010-02-17 17:19:17 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8543 = {
|
2010-02-17 17:19:18 +07:00
|
|
|
.setup = mpc_i2c_setup_8xxx,
|
2010-02-17 17:19:17 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-28 03:59:38 +07:00
|
|
|
static const struct mpc_i2c_data mpc_i2c_data_8544 = {
|
2010-02-17 17:19:18 +07:00
|
|
|
.setup = mpc_i2c_setup_8xxx,
|
2010-02-17 17:19:17 +07:00
|
|
|
};
|
|
|
|
|
|
2008-07-01 06:01:26 +07:00
|
|
|
static const struct of_device_id mpc_i2c_of_match[] = {
|
2010-02-17 17:19:17 +07:00
|
|
|
{.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
|
|
|
|
|
{.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
|
|
|
|
|
{.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
|
2010-02-17 17:19:19 +07:00
|
|
|
{.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
|
2010-02-17 17:19:17 +07:00
|
|
|
{.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
|
|
|
|
|
{.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
|
|
|
|
|
{.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 15:20:55 +07:00
|
|
|
/* Backward compatibility */
|
|
|
|
|
{.compatible = "fsl-i2c", },
|
2008-07-01 06:01:26 +07:00
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
|
|
|
|
|
|
2005-07-28 01:43:26 +07:00
|
|
|
/* Structure for a device driver */
|
2011-02-17 16:43:24 +07:00
|
|
|
static struct platform_driver mpc_i2c_driver = {
|
2008-07-01 06:01:26 +07:00
|
|
|
.probe = fsl_i2c_probe,
|
2012-11-28 03:59:38 +07:00
|
|
|
.remove = fsl_i2c_remove,
|
2010-04-14 06:13:02 +07:00
|
|
|
.driver = {
|
|
|
|
|
.name = DRV_NAME,
|
|
|
|
|
.of_match_table = mpc_i2c_of_match,
|
2013-07-15 09:28:23 +07:00
|
|
|
.pm = MPC_I2C_PM_OPS,
|
2005-11-10 05:32:44 +07:00
|
|
|
},
|
2005-07-28 01:43:26 +07:00
|
|
|
};
|
|
|
|
|
|
2012-01-13 02:32:04 +07:00
|
|
|
module_platform_driver(mpc_i2c_driver);
|
2005-07-28 01:43:26 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
|
2009-04-07 15:20:53 +07:00
|
|
|
MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
|
2010-02-17 17:19:19 +07:00
|
|
|
"MPC824x/83xx/85xx/86xx/512x/52xx processors");
|
2005-04-17 05:20:36 +07:00
|
|
|
MODULE_LICENSE("GPL");
|