mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 20:03:05 +07:00
422 lines
10 KiB
C
422 lines
10 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include <drm/drm_atomic_state_helper.h>
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#include "intel_bw.h"
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#include "intel_drv.h"
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#include "intel_sideband.h"
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/* Parameters for Qclk Geyserville (QGV) */
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struct intel_qgv_point {
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u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
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};
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struct intel_qgv_info {
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struct intel_qgv_point points[3];
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u8 num_points;
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u8 num_channels;
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u8 t_bl;
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enum intel_dram_type dram_type;
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};
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static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_info *qi)
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{
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u32 val = 0;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
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&val, NULL);
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if (ret)
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return ret;
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switch (val & 0xf) {
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case 0:
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qi->dram_type = INTEL_DRAM_DDR4;
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break;
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case 1:
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qi->dram_type = INTEL_DRAM_DDR3;
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break;
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case 2:
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qi->dram_type = INTEL_DRAM_LPDDR3;
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break;
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case 3:
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qi->dram_type = INTEL_DRAM_LPDDR3;
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break;
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default:
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MISSING_CASE(val & 0xf);
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break;
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}
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qi->num_channels = (val & 0xf0) >> 4;
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qi->num_points = (val & 0xf00) >> 8;
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qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
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return 0;
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}
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static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_point *sp,
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int point)
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{
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u32 val = 0, val2;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
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&val, &val2);
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if (ret)
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return ret;
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sp->dclk = val & 0xffff;
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sp->t_rp = (val & 0xff0000) >> 16;
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sp->t_rcd = (val & 0xff000000) >> 24;
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sp->t_rdpre = val2 & 0xff;
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sp->t_ras = (val2 & 0xff00) >> 8;
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sp->t_rc = sp->t_rp + sp->t_ras;
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return 0;
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}
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static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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struct intel_qgv_info *qi)
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{
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int i, ret;
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ret = icl_pcode_read_mem_global_info(dev_priv, qi);
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if (ret)
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return ret;
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if (WARN_ON(qi->num_points > ARRAY_SIZE(qi->points)))
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qi->num_points = ARRAY_SIZE(qi->points);
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for (i = 0; i < qi->num_points; i++) {
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struct intel_qgv_point *sp = &qi->points[i];
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ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
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if (ret)
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return ret;
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DRM_DEBUG_KMS("QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
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i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
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sp->t_rcd, sp->t_rc);
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}
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return 0;
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}
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static int icl_calc_bw(int dclk, int num, int den)
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{
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/* multiples of 16.666MHz (100/6) */
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return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
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}
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static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
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{
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u16 dclk = 0;
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int i;
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for (i = 0; i < qi->num_points; i++)
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dclk = max(dclk, qi->points[i].dclk);
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return dclk;
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}
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struct intel_sa_info {
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u8 deburst, mpagesize, deprogbwlimit, displayrtids;
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};
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static const struct intel_sa_info icl_sa_info = {
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.deburst = 8,
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.mpagesize = 16,
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.deprogbwlimit = 25, /* GB/s */
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.displayrtids = 128,
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};
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static int icl_get_bw_info(struct drm_i915_private *dev_priv)
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{
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struct intel_qgv_info qi = {};
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const struct intel_sa_info *sa = &icl_sa_info;
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bool is_y_tile = true; /* assume y tile may be used */
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int num_channels;
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int deinterleave;
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int ipqdepth, ipqdepthpch;
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int dclk_max;
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int maxdebw;
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int i, ret;
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ret = icl_get_qgv_points(dev_priv, &qi);
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if (ret) {
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DRM_DEBUG_KMS("Failed to get memory subsystem information, ignoring bandwidth limits");
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return ret;
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}
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num_channels = qi.num_channels;
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deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
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dclk_max = icl_sagv_max_dclk(&qi);
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ipqdepthpch = 16;
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maxdebw = min(sa->deprogbwlimit * 1000,
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icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */
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ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
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for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
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struct intel_bw_info *bi = &dev_priv->max_bw[i];
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int clpchgroup;
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int j;
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clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
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bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
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for (j = 0; j < qi.num_points; j++) {
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const struct intel_qgv_point *sp = &qi.points[j];
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int ct, bw;
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/*
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* Max row cycle time
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*
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* FIXME what is the logic behind the
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* assumed burst length?
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*/
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ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
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(clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
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bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
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bi->deratedbw[j] = min(maxdebw,
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bw * 9 / 10); /* 90% */
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DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
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i, j, bi->num_planes, bi->deratedbw[j]);
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}
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if (bi->num_planes == 1)
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break;
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}
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return 0;
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}
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static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
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int num_planes, int qgv_point)
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{
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int i;
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/* Did we initialize the bw limits successfully? */
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if (dev_priv->max_bw[0].num_planes == 0)
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return UINT_MAX;
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for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
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const struct intel_bw_info *bi =
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&dev_priv->max_bw[i];
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if (num_planes >= bi->num_planes)
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return bi->deratedbw[qgv_point];
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}
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return 0;
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}
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void intel_bw_init_hw(struct drm_i915_private *dev_priv)
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{
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if (IS_GEN(dev_priv, 11))
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icl_get_bw_info(dev_priv);
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}
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static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
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int num_planes)
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{
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if (IS_GEN(dev_priv, 11))
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/*
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* FIXME with SAGV disabled maybe we can assume
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* point 1 will always be used? Seems to match
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* the behaviour observed in the wild.
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*/
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return min3(icl_max_bw(dev_priv, num_planes, 0),
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icl_max_bw(dev_priv, num_planes, 1),
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icl_max_bw(dev_priv, num_planes, 2));
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else
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return UINT_MAX;
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}
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static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
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{
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/*
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* We assume cursors are small enough
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* to not not cause bandwidth problems.
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*/
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return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
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}
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static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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unsigned int data_rate = 0;
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enum plane_id plane_id;
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for_each_plane_id_on_crtc(crtc, plane_id) {
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/*
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* We assume cursors are small enough
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* to not not cause bandwidth problems.
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*/
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if (plane_id == PLANE_CURSOR)
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continue;
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data_rate += crtc_state->data_rate[plane_id];
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}
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return data_rate;
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}
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void intel_bw_crtc_update(struct intel_bw_state *bw_state,
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const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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bw_state->data_rate[crtc->pipe] =
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intel_bw_crtc_data_rate(crtc_state);
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bw_state->num_active_planes[crtc->pipe] =
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intel_bw_crtc_num_active_planes(crtc_state);
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DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
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pipe_name(crtc->pipe),
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bw_state->data_rate[crtc->pipe],
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bw_state->num_active_planes[crtc->pipe]);
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}
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static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state)
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{
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unsigned int num_active_planes = 0;
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enum pipe pipe;
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for_each_pipe(dev_priv, pipe)
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num_active_planes += bw_state->num_active_planes[pipe];
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return num_active_planes;
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}
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static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state)
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{
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unsigned int data_rate = 0;
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enum pipe pipe;
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for_each_pipe(dev_priv, pipe)
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data_rate += bw_state->data_rate[pipe];
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return data_rate;
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}
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int intel_bw_atomic_check(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_crtc_state *new_crtc_state, *old_crtc_state;
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struct intel_bw_state *bw_state = NULL;
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unsigned int data_rate, max_data_rate;
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unsigned int num_active_planes;
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struct intel_crtc *crtc;
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int i;
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/* FIXME earlier gens need some checks too */
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if (INTEL_GEN(dev_priv) < 11)
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return 0;
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for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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unsigned int old_data_rate =
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intel_bw_crtc_data_rate(old_crtc_state);
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unsigned int new_data_rate =
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intel_bw_crtc_data_rate(new_crtc_state);
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unsigned int old_active_planes =
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intel_bw_crtc_num_active_planes(old_crtc_state);
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unsigned int new_active_planes =
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intel_bw_crtc_num_active_planes(new_crtc_state);
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/*
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* Avoid locking the bw state when
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* nothing significant has changed.
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*/
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if (old_data_rate == new_data_rate &&
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old_active_planes == new_active_planes)
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continue;
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bw_state = intel_atomic_get_bw_state(state);
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if (IS_ERR(bw_state))
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return PTR_ERR(bw_state);
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bw_state->data_rate[crtc->pipe] = new_data_rate;
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bw_state->num_active_planes[crtc->pipe] = new_active_planes;
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DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n",
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pipe_name(crtc->pipe),
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bw_state->data_rate[crtc->pipe],
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bw_state->num_active_planes[crtc->pipe]);
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}
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if (!bw_state)
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return 0;
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data_rate = intel_bw_data_rate(dev_priv, bw_state);
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num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
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max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
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data_rate = DIV_ROUND_UP(data_rate, 1000);
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if (data_rate > max_data_rate) {
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DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
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data_rate, max_data_rate, num_active_planes);
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return -EINVAL;
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}
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return 0;
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}
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static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj)
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{
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struct intel_bw_state *state;
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state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
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if (!state)
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return NULL;
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__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
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return &state->base;
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}
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static void intel_bw_destroy_state(struct drm_private_obj *obj,
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struct drm_private_state *state)
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{
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kfree(state);
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}
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static const struct drm_private_state_funcs intel_bw_funcs = {
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.atomic_duplicate_state = intel_bw_duplicate_state,
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.atomic_destroy_state = intel_bw_destroy_state,
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};
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int intel_bw_init(struct drm_i915_private *dev_priv)
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{
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struct intel_bw_state *state;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return -ENOMEM;
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drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj,
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&state->base, &intel_bw_funcs);
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return 0;
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}
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