2018-11-06 03:27:27 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2013-09-26 03:38:20 +07:00
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/*
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2018-11-06 03:27:27 +07:00
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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2013-09-26 03:38:20 +07:00
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*/
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/dts-v1/;
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2014-08-14 22:37:22 +07:00
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/* First 4KB has trampoline code for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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2014-04-03 09:31:31 +07:00
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#include "socfpga.dtsi"
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2013-09-26 03:38:20 +07:00
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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2014-10-17 02:43:53 +07:00
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mmc0: dwmmc0@ff704000 {
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2014-02-18 09:31:02 +07:00
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broken-cd;
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2014-08-12 03:57:50 +07:00
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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2014-02-18 09:31:02 +07:00
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};
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2013-09-26 03:38:20 +07:00
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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2016-12-17 06:15:00 +07:00
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&watchdog0 {
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status = "okay";
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};
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