2018-01-10 01:29:55 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-04-11 14:42:24 +07:00
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Exynos SROMC register definitions
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2018-01-10 01:29:55 +07:00
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*/
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2016-04-11 14:42:24 +07:00
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#ifndef __EXYNOS_SROM_H
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#define __EXYNOS_SROM_H __FILE__
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#define EXYNOS_SROMREG(x) (x)
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#define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0)
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#define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4)
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#define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8)
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#define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc)
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#define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10)
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#define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14)
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#define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0
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#define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1
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#define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2
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#define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3
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#define EXYNOS_SROM_BW__CS_MASK 0xf
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#define EXYNOS_SROM_BW__NCS0__SHIFT 0
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#define EXYNOS_SROM_BW__NCS1__SHIFT 4
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#define EXYNOS_SROM_BW__NCS2__SHIFT 8
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#define EXYNOS_SROM_BW__NCS3__SHIFT 12
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#define EXYNOS_SROM_BW__NCS4__SHIFT 16
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#define EXYNOS_SROM_BW__NCS5__SHIFT 20
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/* applies to same to BCS0 - BCS3 */
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#define EXYNOS_SROM_BCX__PMC__SHIFT 0
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#define EXYNOS_SROM_BCX__TACP__SHIFT 4
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#define EXYNOS_SROM_BCX__TCAH__SHIFT 8
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#define EXYNOS_SROM_BCX__TCOH__SHIFT 12
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#define EXYNOS_SROM_BCX__TACC__SHIFT 16
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#define EXYNOS_SROM_BCX__TCOS__SHIFT 24
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#define EXYNOS_SROM_BCX__TACS__SHIFT 28
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#endif /* __EXYNOS_SROM_H */
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