2012-03-05 18:49:27 +07:00
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/*
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* Based on arch/arm/kernel/setup.c
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*
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* Copyright (C) 1995-2001 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/utsname.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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2014-04-03 23:48:54 +07:00
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#include <linux/cache.h>
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2012-03-05 18:49:27 +07:00
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/screen_info.h>
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#include <linux/init.h>
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#include <linux/kexec.h>
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#include <linux/crash_dump.h>
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#include <linux/root_dev.h>
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2013-02-08 19:18:15 +07:00
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#include <linux/clk-provider.h>
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2012-03-05 18:49:27 +07:00
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/fs.h>
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#include <linux/proc_fs.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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2012-12-08 00:47:17 +07:00
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#include <linux/of_platform.h>
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2014-04-16 08:59:30 +07:00
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#include <linux/efi.h>
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2012-03-05 18:49:27 +07:00
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2014-04-08 05:39:52 +07:00
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#include <asm/fixmap.h>
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2012-03-05 18:49:27 +07:00
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#include <asm/cputype.h>
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#include <asm/elf.h>
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#include <asm/cputable.h>
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2013-10-25 02:30:17 +07:00
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#include <asm/cpu_ops.h>
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2012-03-05 18:49:27 +07:00
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#include <asm/sections.h>
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#include <asm/setup.h>
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2012-08-29 15:47:19 +07:00
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#include <asm/smp_plat.h>
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2012-03-05 18:49:27 +07:00
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/traps.h>
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#include <asm/memblock.h>
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2012-12-19 00:53:14 +07:00
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#include <asm/psci.h>
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2014-04-16 08:59:30 +07:00
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#include <asm/efi.h>
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2012-03-05 18:49:27 +07:00
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unsigned int processor_id;
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EXPORT_SYMBOL(processor_id);
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2013-09-18 22:14:28 +07:00
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unsigned long elf_hwcap __read_mostly;
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2012-03-05 18:49:27 +07:00
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EXPORT_SYMBOL_GPL(elf_hwcap);
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2013-08-13 21:57:53 +07:00
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#ifdef CONFIG_COMPAT
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#define COMPAT_ELF_HWCAP_DEFAULT \
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(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
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COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
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COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
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COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
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COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
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unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
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2014-03-03 14:34:45 +07:00
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unsigned int compat_elf_hwcap2 __read_mostly;
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2013-08-13 21:57:53 +07:00
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#endif
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2012-03-05 18:49:27 +07:00
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static const char *cpu_name;
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static const char *machine_name;
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phys_addr_t __fdt_pointer __initdata;
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/*
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* Standard memory resources
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*/
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static struct resource mem_res[] = {
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{
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.name = "Kernel code",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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},
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{
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.name = "Kernel data",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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}
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};
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#define kernel_code mem_res[0]
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#define kernel_data mem_res[1]
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void __init early_print(const char *str, ...)
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{
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char buf[256];
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va_list ap;
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va_start(ap, str);
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vsnprintf(buf, sizeof(buf), str, ap);
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va_end(ap);
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printk("%s", buf);
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}
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2013-11-06 01:10:47 +07:00
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void __init smp_setup_processor_id(void)
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{
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/*
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* clear __my_cpu_offset on boot CPU to avoid hang caused by
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* using percpu variable early, for example, lockdep will
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* access percpu variable inside lock_release
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*/
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set_my_cpu_offset(0);
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}
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2013-10-21 19:29:42 +07:00
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bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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{
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return phys_id == cpu_logical_map(cpu);
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}
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arm64: kernel: build MPIDR_EL1 hash function data structure
On ARM64 SMP systems, cores are identified by their MPIDR_EL1 register.
The MPIDR_EL1 guidelines in the ARM ARM do not provide strict enforcement of
MPIDR_EL1 layout, only recommendations that, if followed, split the MPIDR_EL1
on ARM 64 bit platforms in four affinity levels. In multi-cluster
systems like big.LITTLE, if the affinity guidelines are followed, the
MPIDR_EL1 can not be considered a linear index. This means that the
association between logical CPU in the kernel and the HW CPU identifier
becomes somewhat more complicated requiring methods like hashing to
associate a given MPIDR_EL1 to a CPU logical index, in order for the look-up
to be carried out in an efficient and scalable way.
This patch provides a function in the kernel that starting from the
cpu_logical_map, implement collision-free hashing of MPIDR_EL1 values by
checking all significative bits of MPIDR_EL1 affinity level bitfields.
The hashing can then be carried out through bits shifting and ORing; the
resulting hash algorithm is a collision-free though not minimal hash that can
be executed with few assembly instructions. The mpidr_el1 is filtered through a
mpidr mask that is built by checking all bits that toggle in the set of
MPIDR_EL1s corresponding to possible CPUs. Bits that do not toggle do not
carry information so they do not contribute to the resulting hash.
Pseudo code:
/* check all bits that toggle, so they are required */
for (i = 1, mpidr_el1_mask = 0; i < num_possible_cpus(); i++)
mpidr_el1_mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
/*
* Build shifts to be applied to aff0, aff1, aff2, aff3 values to hash the
* mpidr_el1
* fls() returns the last bit set in a word, 0 if none
* ffs() returns the first bit set in a word, 0 if none
*/
fs0 = mpidr_el1_mask[7:0] ? ffs(mpidr_el1_mask[7:0]) - 1 : 0;
fs1 = mpidr_el1_mask[15:8] ? ffs(mpidr_el1_mask[15:8]) - 1 : 0;
fs2 = mpidr_el1_mask[23:16] ? ffs(mpidr_el1_mask[23:16]) - 1 : 0;
fs3 = mpidr_el1_mask[39:32] ? ffs(mpidr_el1_mask[39:32]) - 1 : 0;
ls0 = fls(mpidr_el1_mask[7:0]);
ls1 = fls(mpidr_el1_mask[15:8]);
ls2 = fls(mpidr_el1_mask[23:16]);
ls3 = fls(mpidr_el1_mask[39:32]);
bits0 = ls0 - fs0;
bits1 = ls1 - fs1;
bits2 = ls2 - fs2;
bits3 = ls3 - fs3;
aff0_shift = fs0;
aff1_shift = 8 + fs1 - bits0;
aff2_shift = 16 + fs2 - (bits0 + bits1);
aff3_shift = 32 + fs3 - (bits0 + bits1 + bits2);
u32 hash(u64 mpidr_el1) {
u32 l[4];
u64 mpidr_el1_masked = mpidr_el1 & mpidr_el1_mask;
l[0] = mpidr_el1_masked & 0xff;
l[1] = mpidr_el1_masked & 0xff00;
l[2] = mpidr_el1_masked & 0xff0000;
l[3] = mpidr_el1_masked & 0xff00000000;
return (l[0] >> aff0_shift | l[1] >> aff1_shift | l[2] >> aff2_shift |
l[3] >> aff3_shift);
}
The hashing algorithm relies on the inherent properties set in the ARM ARM
recommendations for the MPIDR_EL1. Exotic configurations, where for instance
the MPIDR_EL1 values at a given affinity level have large holes, can end up
requiring big hash tables since the compression of values that can be achieved
through shifting is somewhat crippled when holes are present. Kernel warns if
the number of buckets of the resulting hash table exceeds the number of
possible CPUs by a factor of 4, which is a symptom of a very sparse HW
MPIDR_EL1 configuration.
The hash algorithm is quite simple and can easily be implemented in assembly
code, to be used in code paths where the kernel virtual address space is
not set-up (ie cpu_resume) and instruction and data fetches are strongly
ordered so code must be compact and must carry out few data accesses.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2013-05-16 16:32:09 +07:00
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struct mpidr_hash mpidr_hash;
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#ifdef CONFIG_SMP
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/**
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* smp_build_mpidr_hash - Pre-compute shifts required at each affinity
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* level in order to build a linear index from an
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* MPIDR value. Resulting algorithm is a collision
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* free hash carried out through shifting and ORing
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*/
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static void __init smp_build_mpidr_hash(void)
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{
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u32 i, affinity, fs[4], bits[4], ls;
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u64 mask = 0;
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/*
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* Pre-scan the list of MPIDRS and filter out bits that do
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* not contribute to affinity levels, ie they never toggle.
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*/
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for_each_possible_cpu(i)
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mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
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pr_debug("mask of set bits %#llx\n", mask);
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/*
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* Find and stash the last and first bit set at all affinity levels to
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* check how many bits are required to represent them.
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*/
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for (i = 0; i < 4; i++) {
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affinity = MPIDR_AFFINITY_LEVEL(mask, i);
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/*
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* Find the MSB bit and LSB bits position
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* to determine how many bits are required
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* to express the affinity level.
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*/
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ls = fls(affinity);
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fs[i] = affinity ? ffs(affinity) - 1 : 0;
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bits[i] = ls - fs[i];
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}
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/*
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* An index can be created from the MPIDR_EL1 by isolating the
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* significant bits at each affinity level and by shifting
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* them in order to compress the 32 bits values space to a
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* compressed set of values. This is equivalent to hashing
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* the MPIDR_EL1 through shifting and ORing. It is a collision free
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* hash though not minimal since some levels might contain a number
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* of CPUs that is not an exact power of 2 and their bit
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* representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
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*/
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mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
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mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
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mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
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(bits[1] + bits[0]);
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mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
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fs[3] - (bits[2] + bits[1] + bits[0]);
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mpidr_hash.mask = mask;
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mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
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pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
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mpidr_hash.shift_aff[0],
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mpidr_hash.shift_aff[1],
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mpidr_hash.shift_aff[2],
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mpidr_hash.shift_aff[3],
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mpidr_hash.mask,
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mpidr_hash.bits);
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/*
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* 4x is an arbitrary value used to warn on a hash table much bigger
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* than expected on most systems.
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*/
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if (mpidr_hash_size() > 4 * num_possible_cpus())
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pr_warn("Large number of MPIDR hash buckets detected\n");
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__flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
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}
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#endif
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2012-03-05 18:49:27 +07:00
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static void __init setup_processor(void)
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{
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struct cpu_info *cpu_info;
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2013-12-17 04:04:36 +07:00
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u64 features, block;
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2014-04-03 23:48:54 +07:00
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u32 cwg;
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int cls;
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2012-03-05 18:49:27 +07:00
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cpu_info = lookup_processor_type(read_cpuid_id());
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if (!cpu_info) {
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printk("CPU configuration botched (ID %08x), unable to continue.\n",
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read_cpuid_id());
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while (1);
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}
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cpu_name = cpu_info->cpu_name;
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printk("CPU: %s [%08x] revision %d\n",
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cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
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2013-10-11 20:52:11 +07:00
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sprintf(init_utsname()->machine, ELF_PLATFORM);
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2012-03-05 18:49:27 +07:00
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elf_hwcap = 0;
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2013-12-17 04:04:36 +07:00
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2014-04-03 23:48:54 +07:00
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/*
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* Check for sane CTR_EL0.CWG value.
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*/
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cwg = cache_type_cwg();
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cls = cache_line_size();
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if (!cwg)
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pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
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cls);
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if (L1_CACHE_BYTES < cls)
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pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
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L1_CACHE_BYTES, cls);
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2013-12-17 04:04:36 +07:00
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/*
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* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
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* The blocks we test below represent incremental functionality
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* for non-negative values. Negative values are reserved.
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*/
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features = read_cpuid(ID_AA64ISAR0_EL1);
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block = (features >> 4) & 0xf;
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if (!(block & 0x8)) {
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switch (block) {
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default:
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case 2:
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elf_hwcap |= HWCAP_PMULL;
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case 1:
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elf_hwcap |= HWCAP_AES;
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case 0:
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break;
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}
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}
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block = (features >> 8) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA1;
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block = (features >> 12) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA2;
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block = (features >> 16) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_CRC32;
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2014-03-03 14:34:46 +07:00
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#ifdef CONFIG_COMPAT
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/*
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* ID_ISAR5_EL1 carries similar information as above, but pertaining to
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* the Aarch32 32-bit execution state.
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*/
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features = read_cpuid(ID_ISAR5_EL1);
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block = (features >> 4) & 0xf;
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if (!(block & 0x8)) {
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switch (block) {
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default:
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case 2:
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compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
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case 1:
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|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
block = (features >> 8) & 0xf;
|
|
|
|
if (block && !(block & 0x8))
|
|
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
|
|
|
|
|
|
|
|
block = (features >> 12) & 0xf;
|
|
|
|
if (block && !(block & 0x8))
|
|
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
|
|
|
|
|
|
|
|
block = (features >> 16) & 0xf;
|
|
|
|
if (block && !(block & 0x8))
|
|
|
|
compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
|
|
|
|
#endif
|
2012-03-05 18:49:27 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init setup_machine_fdt(phys_addr_t dt_phys)
|
|
|
|
{
|
2013-08-26 22:14:32 +07:00
|
|
|
if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
|
2012-03-05 18:49:27 +07:00
|
|
|
early_print("\n"
|
|
|
|
"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
|
2013-08-26 22:14:32 +07:00
|
|
|
"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
|
2012-03-05 18:49:27 +07:00
|
|
|
"\nPlease check your bootloader.\n",
|
2013-08-26 22:14:32 +07:00
|
|
|
dt_phys, phys_to_virt(dt_phys));
|
2012-03-05 18:49:27 +07:00
|
|
|
|
|
|
|
while (true)
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
2013-08-28 09:44:37 +07:00
|
|
|
machine_name = of_flat_dt_get_machine_name();
|
2012-03-05 18:49:27 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Limit the memory size that was specified via FDT.
|
|
|
|
*/
|
|
|
|
static int __init early_mem(char *p)
|
|
|
|
{
|
|
|
|
phys_addr_t limit;
|
|
|
|
|
|
|
|
if (!p)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
limit = memparse(p, &p) & PAGE_MASK;
|
|
|
|
pr_notice("Memory limited to %lldMB\n", limit >> 20);
|
|
|
|
|
|
|
|
memblock_enforce_memory_limit(limit);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
early_param("mem", early_mem);
|
|
|
|
|
|
|
|
static void __init request_standard_resources(void)
|
|
|
|
{
|
|
|
|
struct memblock_region *region;
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
kernel_code.start = virt_to_phys(_text);
|
|
|
|
kernel_code.end = virt_to_phys(_etext - 1);
|
|
|
|
kernel_data.start = virt_to_phys(_sdata);
|
|
|
|
kernel_data.end = virt_to_phys(_end - 1);
|
|
|
|
|
|
|
|
for_each_memblock(memory, region) {
|
|
|
|
res = alloc_bootmem_low(sizeof(*res));
|
|
|
|
res->name = "System RAM";
|
|
|
|
res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
|
|
|
|
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
|
|
|
|
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
|
|
|
|
|
|
|
request_resource(&iomem_resource, res);
|
|
|
|
|
|
|
|
if (kernel_code.start >= res->start &&
|
|
|
|
kernel_code.end <= res->end)
|
|
|
|
request_resource(res, &kernel_code);
|
|
|
|
if (kernel_data.start >= res->start &&
|
|
|
|
kernel_data.end <= res->end)
|
|
|
|
request_resource(res, &kernel_data);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-29 15:47:19 +07:00
|
|
|
u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
|
|
|
|
|
2012-03-05 18:49:27 +07:00
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
|
|
{
|
2013-11-21 21:46:17 +07:00
|
|
|
/*
|
|
|
|
* Unmask asynchronous aborts early to catch possible system errors.
|
|
|
|
*/
|
|
|
|
local_async_enable();
|
|
|
|
|
2012-03-05 18:49:27 +07:00
|
|
|
setup_processor();
|
|
|
|
|
|
|
|
setup_machine_fdt(__fdt_pointer);
|
|
|
|
|
|
|
|
init_mm.start_code = (unsigned long) _text;
|
|
|
|
init_mm.end_code = (unsigned long) _etext;
|
|
|
|
init_mm.end_data = (unsigned long) _edata;
|
|
|
|
init_mm.brk = (unsigned long) _end;
|
|
|
|
|
|
|
|
*cmdline_p = boot_command_line;
|
|
|
|
|
2014-04-08 05:39:52 +07:00
|
|
|
early_ioremap_init();
|
2014-04-08 05:39:51 +07:00
|
|
|
|
2012-03-05 18:49:27 +07:00
|
|
|
parse_early_param();
|
|
|
|
|
2014-04-16 08:59:30 +07:00
|
|
|
efi_init();
|
2012-03-05 18:49:27 +07:00
|
|
|
arm64_memblock_init();
|
|
|
|
|
|
|
|
paging_init();
|
|
|
|
request_standard_resources();
|
|
|
|
|
2014-04-16 08:59:30 +07:00
|
|
|
efi_idmap_init();
|
|
|
|
|
2012-03-05 18:49:27 +07:00
|
|
|
unflatten_device_tree();
|
|
|
|
|
2012-12-19 00:53:14 +07:00
|
|
|
psci_init();
|
|
|
|
|
2012-08-29 15:47:19 +07:00
|
|
|
cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
|
2013-10-25 02:30:17 +07:00
|
|
|
cpu_read_bootcpu_ops();
|
2012-03-05 18:49:27 +07:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
smp_init_cpus();
|
arm64: kernel: build MPIDR_EL1 hash function data structure
On ARM64 SMP systems, cores are identified by their MPIDR_EL1 register.
The MPIDR_EL1 guidelines in the ARM ARM do not provide strict enforcement of
MPIDR_EL1 layout, only recommendations that, if followed, split the MPIDR_EL1
on ARM 64 bit platforms in four affinity levels. In multi-cluster
systems like big.LITTLE, if the affinity guidelines are followed, the
MPIDR_EL1 can not be considered a linear index. This means that the
association between logical CPU in the kernel and the HW CPU identifier
becomes somewhat more complicated requiring methods like hashing to
associate a given MPIDR_EL1 to a CPU logical index, in order for the look-up
to be carried out in an efficient and scalable way.
This patch provides a function in the kernel that starting from the
cpu_logical_map, implement collision-free hashing of MPIDR_EL1 values by
checking all significative bits of MPIDR_EL1 affinity level bitfields.
The hashing can then be carried out through bits shifting and ORing; the
resulting hash algorithm is a collision-free though not minimal hash that can
be executed with few assembly instructions. The mpidr_el1 is filtered through a
mpidr mask that is built by checking all bits that toggle in the set of
MPIDR_EL1s corresponding to possible CPUs. Bits that do not toggle do not
carry information so they do not contribute to the resulting hash.
Pseudo code:
/* check all bits that toggle, so they are required */
for (i = 1, mpidr_el1_mask = 0; i < num_possible_cpus(); i++)
mpidr_el1_mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
/*
* Build shifts to be applied to aff0, aff1, aff2, aff3 values to hash the
* mpidr_el1
* fls() returns the last bit set in a word, 0 if none
* ffs() returns the first bit set in a word, 0 if none
*/
fs0 = mpidr_el1_mask[7:0] ? ffs(mpidr_el1_mask[7:0]) - 1 : 0;
fs1 = mpidr_el1_mask[15:8] ? ffs(mpidr_el1_mask[15:8]) - 1 : 0;
fs2 = mpidr_el1_mask[23:16] ? ffs(mpidr_el1_mask[23:16]) - 1 : 0;
fs3 = mpidr_el1_mask[39:32] ? ffs(mpidr_el1_mask[39:32]) - 1 : 0;
ls0 = fls(mpidr_el1_mask[7:0]);
ls1 = fls(mpidr_el1_mask[15:8]);
ls2 = fls(mpidr_el1_mask[23:16]);
ls3 = fls(mpidr_el1_mask[39:32]);
bits0 = ls0 - fs0;
bits1 = ls1 - fs1;
bits2 = ls2 - fs2;
bits3 = ls3 - fs3;
aff0_shift = fs0;
aff1_shift = 8 + fs1 - bits0;
aff2_shift = 16 + fs2 - (bits0 + bits1);
aff3_shift = 32 + fs3 - (bits0 + bits1 + bits2);
u32 hash(u64 mpidr_el1) {
u32 l[4];
u64 mpidr_el1_masked = mpidr_el1 & mpidr_el1_mask;
l[0] = mpidr_el1_masked & 0xff;
l[1] = mpidr_el1_masked & 0xff00;
l[2] = mpidr_el1_masked & 0xff0000;
l[3] = mpidr_el1_masked & 0xff00000000;
return (l[0] >> aff0_shift | l[1] >> aff1_shift | l[2] >> aff2_shift |
l[3] >> aff3_shift);
}
The hashing algorithm relies on the inherent properties set in the ARM ARM
recommendations for the MPIDR_EL1. Exotic configurations, where for instance
the MPIDR_EL1 values at a given affinity level have large holes, can end up
requiring big hash tables since the compression of values that can be achieved
through shifting is somewhat crippled when holes are present. Kernel warns if
the number of buckets of the resulting hash table exceeds the number of
possible CPUs by a factor of 4, which is a symptom of a very sparse HW
MPIDR_EL1 configuration.
The hash algorithm is quite simple and can easily be implemented in assembly
code, to be used in code paths where the kernel virtual address space is
not set-up (ie cpu_resume) and instruction and data fetches are strongly
ordered so code must be compact and must carry out few data accesses.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2013-05-16 16:32:09 +07:00
|
|
|
smp_build_mpidr_hash();
|
2012-03-05 18:49:27 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_VT
|
|
|
|
#if defined(CONFIG_VGA_CONSOLE)
|
|
|
|
conswitchp = &vga_con;
|
|
|
|
#elif defined(CONFIG_DUMMY_CONSOLE)
|
|
|
|
conswitchp = &dummy_con;
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2013-05-14 16:51:18 +07:00
|
|
|
static int __init arm64_device_init(void)
|
2013-02-08 19:18:15 +07:00
|
|
|
{
|
2013-05-14 16:51:18 +07:00
|
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
2013-02-08 19:18:15 +07:00
|
|
|
return 0;
|
|
|
|
}
|
2014-04-25 21:31:45 +07:00
|
|
|
arch_initcall_sync(arm64_device_init);
|
2013-02-08 19:18:15 +07:00
|
|
|
|
2012-03-05 18:49:27 +07:00
|
|
|
static DEFINE_PER_CPU(struct cpu, cpu_data);
|
|
|
|
|
|
|
|
static int __init topology_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_possible_cpu(i) {
|
|
|
|
struct cpu *cpu = &per_cpu(cpu_data, i);
|
|
|
|
cpu->hotpluggable = 1;
|
|
|
|
register_cpu(cpu, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
subsys_initcall(topology_init);
|
|
|
|
|
|
|
|
static const char *hwcap_str[] = {
|
|
|
|
"fp",
|
|
|
|
"asimd",
|
2013-08-13 21:57:53 +07:00
|
|
|
"evtstrm",
|
2013-12-17 04:04:36 +07:00
|
|
|
"aes",
|
|
|
|
"pmull",
|
|
|
|
"sha1",
|
|
|
|
"sha2",
|
|
|
|
"crc32",
|
2012-03-05 18:49:27 +07:00
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static int c_show(struct seq_file *m, void *v)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
|
|
|
|
cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
|
|
|
|
|
|
|
|
for_each_online_cpu(i) {
|
|
|
|
/*
|
|
|
|
* glibc reads /proc/cpuinfo to determine the number of
|
|
|
|
* online processors, looking for lines beginning with
|
|
|
|
* "processor". Give glibc what it expects.
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
seq_printf(m, "processor\t: %d\n", i);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dump out the processor features */
|
|
|
|
seq_puts(m, "Features\t: ");
|
|
|
|
|
|
|
|
for (i = 0; hwcap_str[i]; i++)
|
|
|
|
if (elf_hwcap & (1 << i))
|
|
|
|
seq_printf(m, "%s ", hwcap_str[i]);
|
|
|
|
|
|
|
|
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
|
|
|
|
seq_printf(m, "CPU architecture: AArch64\n");
|
|
|
|
seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
|
|
|
|
seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
|
|
|
|
seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
|
|
|
|
|
|
|
|
seq_puts(m, "\n");
|
|
|
|
|
|
|
|
seq_printf(m, "Hardware\t: %s\n", machine_name);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *c_start(struct seq_file *m, loff_t *pos)
|
|
|
|
{
|
|
|
|
return *pos < 1 ? (void *)1 : NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
|
|
|
|
{
|
|
|
|
++*pos;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void c_stop(struct seq_file *m, void *v)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct seq_operations cpuinfo_op = {
|
|
|
|
.start = c_start,
|
|
|
|
.next = c_next,
|
|
|
|
.stop = c_stop,
|
|
|
|
.show = c_show
|
|
|
|
};
|