2018-05-10 01:06:04 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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2014-11-04 01:07:35 +07:00
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*/
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#ifndef _LINUX_CORESIGHT_H
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#define _LINUX_CORESIGHT_H
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#include <linux/device.h>
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2016-02-18 07:51:57 +07:00
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#include <linux/perf_event.h>
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2015-07-31 22:37:30 +07:00
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#include <linux/sched.h>
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2014-11-04 01:07:35 +07:00
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/* Peripheral id registers (0xFD0-0xFEC) */
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#define CORESIGHT_PERIPHIDR4 0xfd0
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#define CORESIGHT_PERIPHIDR5 0xfd4
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#define CORESIGHT_PERIPHIDR6 0xfd8
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#define CORESIGHT_PERIPHIDR7 0xfdC
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#define CORESIGHT_PERIPHIDR0 0xfe0
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#define CORESIGHT_PERIPHIDR1 0xfe4
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#define CORESIGHT_PERIPHIDR2 0xfe8
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#define CORESIGHT_PERIPHIDR3 0xfeC
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/* Component id registers (0xFF0-0xFFC) */
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#define CORESIGHT_COMPIDR0 0xff0
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#define CORESIGHT_COMPIDR1 0xff4
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#define CORESIGHT_COMPIDR2 0xff8
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#define CORESIGHT_COMPIDR3 0xffC
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#define ETM_ARCH_V3_3 0x23
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#define ETM_ARCH_V3_5 0x25
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#define PFT_ARCH_V1_0 0x30
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#define PFT_ARCH_V1_1 0x31
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#define CORESIGHT_UNLOCK 0xc5acce55
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extern struct bus_type coresight_bustype;
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enum coresight_dev_type {
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CORESIGHT_DEV_TYPE_NONE,
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CORESIGHT_DEV_TYPE_SINK,
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CORESIGHT_DEV_TYPE_LINK,
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CORESIGHT_DEV_TYPE_LINKSINK,
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CORESIGHT_DEV_TYPE_SOURCE,
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coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
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CORESIGHT_DEV_TYPE_HELPER,
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2014-11-04 01:07:35 +07:00
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};
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enum coresight_dev_subtype_sink {
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CORESIGHT_DEV_SUBTYPE_SINK_NONE,
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CORESIGHT_DEV_SUBTYPE_SINK_PORT,
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CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
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};
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enum coresight_dev_subtype_link {
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CORESIGHT_DEV_SUBTYPE_LINK_NONE,
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CORESIGHT_DEV_SUBTYPE_LINK_MERG,
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CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
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CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
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};
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enum coresight_dev_subtype_source {
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CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
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CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
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CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
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CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
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};
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coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
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enum coresight_dev_subtype_helper {
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CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
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2018-07-12 02:40:31 +07:00
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CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
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coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
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};
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2014-11-04 01:07:35 +07:00
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/**
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2018-07-12 02:40:29 +07:00
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* union coresight_dev_subtype - further characterisation of a type
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2014-11-04 01:07:35 +07:00
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* @sink_subtype: type of sink this component is, as defined
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2018-07-12 02:40:29 +07:00
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* by @coresight_dev_subtype_sink.
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2014-11-04 01:07:35 +07:00
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* @link_subtype: type of link this component is, as defined
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2018-07-12 02:40:29 +07:00
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* by @coresight_dev_subtype_link.
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2014-11-04 01:07:35 +07:00
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* @source_subtype: type of source this component is, as defined
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2018-07-12 02:40:29 +07:00
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* by @coresight_dev_subtype_source.
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coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
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* @helper_subtype: type of helper this component is, as defined
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* by @coresight_dev_subtype_helper.
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2014-11-04 01:07:35 +07:00
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*/
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2018-07-12 02:40:29 +07:00
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union coresight_dev_subtype {
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/* We have some devices which acts as LINK and SINK */
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struct {
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enum coresight_dev_subtype_sink sink_subtype;
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enum coresight_dev_subtype_link link_subtype;
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};
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2014-11-04 01:07:35 +07:00
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enum coresight_dev_subtype_source source_subtype;
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coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
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enum coresight_dev_subtype_helper helper_subtype;
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2014-11-04 01:07:35 +07:00
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};
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/**
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* struct coresight_platform_data - data harvested from the DT specification
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* @cpu: the CPU a source belongs to. Only applicable for ETM/PTMs.
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* @name: name of the component as shown under sysfs.
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* @nr_inport: number of input ports for this component.
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* @nr_outport: number of output ports for this component.
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2018-09-21 02:17:42 +07:00
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* @conns: Array of nr_outport connections from this component
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2014-11-04 01:07:35 +07:00
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*/
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struct coresight_platform_data {
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int cpu;
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const char *name;
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int nr_inport;
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int nr_outport;
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2018-09-21 02:17:42 +07:00
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struct coresight_connection *conns;
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2014-11-04 01:07:35 +07:00
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};
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/**
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* struct coresight_desc - description of a component required from drivers
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* @type: as defined by @coresight_dev_type.
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* @subtype: as defined by @coresight_dev_subtype.
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* @ops: generic operations for this component, as defined
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by @coresight_ops.
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* @pdata: platform data collected from DT.
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* @dev: The device entity associated to this component.
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2014-11-13 15:42:48 +07:00
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* @groups: operations specific to this component. These will end up
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2014-11-04 01:07:35 +07:00
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in the component's sysfs sub-directory.
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*/
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struct coresight_desc {
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enum coresight_dev_type type;
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2018-07-12 02:40:29 +07:00
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union coresight_dev_subtype subtype;
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2014-11-04 01:07:35 +07:00
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const struct coresight_ops *ops;
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struct coresight_platform_data *pdata;
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struct device *dev;
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const struct attribute_group **groups;
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};
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/**
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* struct coresight_connection - representation of a single connection
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* @outport: a connection's output port number.
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* @chid_name: remote component's name.
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* @child_port: remote component's port number @output is connected to.
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* @child_dev: a @coresight_device representation of the component
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connected to @outport.
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*/
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struct coresight_connection {
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int outport;
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const char *child_name;
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int child_port;
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struct coresight_device *child_dev;
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};
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/**
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* struct coresight_device - representation of a device as used by the framework
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2014-11-13 15:42:48 +07:00
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* @conns: array of coresight_connections associated to this component.
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2014-11-04 01:07:35 +07:00
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* @nr_inport: number of input port associated to this component.
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* @nr_outport: number of output port associated to this component.
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* @type: as defined by @coresight_dev_type.
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* @subtype: as defined by @coresight_dev_subtype.
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* @ops: generic operations for this component, as defined
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by @coresight_ops.
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* @dev: The device entity associated to this component.
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* @refcnt: keep track of what is in use.
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* @orphan: true if the component has connections that haven't been linked.
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* @enable: 'true' if component is currently part of an active path.
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* @activated: 'true' only if a _sink_ has been activated. A sink can be
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coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-02-01 01:47:09 +07:00
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* activated but not yet enabled. Enabling for a _sink_
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* appens when a source has been selected for that it.
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* @ea: Device attribute for sink representation under PMU directory.
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2014-11-04 01:07:35 +07:00
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*/
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struct coresight_device {
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struct coresight_connection *conns;
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int nr_inport;
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int nr_outport;
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enum coresight_dev_type type;
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2018-07-12 02:40:29 +07:00
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union coresight_dev_subtype subtype;
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2014-11-04 01:07:35 +07:00
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const struct coresight_ops *ops;
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struct device dev;
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atomic_t *refcnt;
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bool orphan;
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bool enable; /* true only if configured as part of a path */
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coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-02-01 01:47:09 +07:00
|
|
|
/* sink specific fields */
|
2014-11-04 01:07:35 +07:00
|
|
|
bool activated; /* true only if a sink is part of a path */
|
coresight: perf: Add "sinks" group to PMU directory
Add a "sinks" directory entry so that users can see all the sinks
available in the system in a single place. Individual sink are added
as they are registered with the coresight bus.
Committer tests:
Test built on a ubuntu 18.04 container with a cross build environment to
arm64, the new field is there, need to find a machine with this feature
to do further testing in the future.
root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_LINKS_AND_SINKS=y
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
CONFIG_CORESIGHT_CATU=y
CONFIG_CORESIGHT_SINK_TPIU=y
CONFIG_CORESIGHT_SINK_ETBV10=y
CONFIG_CORESIGHT_SOURCE_ETM4X=y
CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
CONFIG_CORESIGHT_STM=y
CONFIG_CORESIGHT_CPU_DEBUG=m
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
.../coresight/coresight-catu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.mod.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-cpu-debug.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etb10.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm-perf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x-sysfs.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-etm4x.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-funnel.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-stm.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etf.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc-etr.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tmc.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight-tpiu.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
.../coresight/of_coresight.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
root@d15263e5734a:/git/perf#
root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
struct coresight_device {
struct coresight_connection * conns; /* 0 8 */
int nr_inport; /* 8 4 */
int nr_outport; /* 12 4 */
enum coresight_dev_type type; /* 16 4 */
union coresight_dev_subtype subtype; /* 20 8 */
/* XXX 4 bytes hole, try to pack */
const struct coresight_ops * ops; /* 32 8 */
struct device dev; /* 40 1408 */
/* XXX last struct has 7 bytes of padding */
/* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
atomic_t * refcnt; /* 1448 8 */
bool orphan; /* 1456 1 */
bool enable; /* 1457 1 */
bool activated; /* 1458 1 */
/* XXX 5 bytes hole, try to pack */
struct dev_ext_attribute * ea; /* 1464 8 */
/* size: 1472, cachelines: 23, members: 12 */
/* sum members: 1463, holes: 2, sum holes: 9 */
/* paddings: 1, sum paddings: 7 */
};
root@d15263e5734a:/git/perf#
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-s390@vger.kernel.org
Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2019-02-01 01:47:09 +07:00
|
|
|
struct dev_ext_attribute *ea;
|
2014-11-04 01:07:35 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
|
|
|
|
|
|
|
|
#define source_ops(csdev) csdev->ops->source_ops
|
|
|
|
#define sink_ops(csdev) csdev->ops->sink_ops
|
|
|
|
#define link_ops(csdev) csdev->ops->link_ops
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
|
|
|
#define helper_ops(csdev) csdev->ops->helper_ops
|
2014-11-04 01:07:35 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct coresight_ops_sink - basic operations for a sink
|
|
|
|
* Operations available for sinks
|
2016-02-18 07:52:00 +07:00
|
|
|
* @enable: enables the sink.
|
|
|
|
* @disable: disables the sink.
|
|
|
|
* @alloc_buffer: initialises perf's ring buffer for trace collection.
|
|
|
|
* @free_buffer: release memory allocated in @get_config.
|
|
|
|
* @update_buffer: update buffer pointers after a trace session.
|
2014-11-04 01:07:35 +07:00
|
|
|
*/
|
|
|
|
struct coresight_ops_sink {
|
2018-09-21 02:17:56 +07:00
|
|
|
int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
|
2019-04-26 02:52:55 +07:00
|
|
|
int (*disable)(struct coresight_device *csdev);
|
2019-04-26 02:53:01 +07:00
|
|
|
void *(*alloc_buffer)(struct coresight_device *csdev,
|
|
|
|
struct perf_event *event, void **pages,
|
|
|
|
int nr_pages, bool overwrite);
|
2016-02-18 07:52:00 +07:00
|
|
|
void (*free_buffer)(void *config);
|
2018-09-21 02:17:54 +07:00
|
|
|
unsigned long (*update_buffer)(struct coresight_device *csdev,
|
2016-02-18 07:52:00 +07:00
|
|
|
struct perf_output_handle *handle,
|
|
|
|
void *sink_config);
|
2014-11-04 01:07:35 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct coresight_ops_link - basic operations for a link
|
|
|
|
* Operations available for links.
|
|
|
|
* @enable: enables flow between iport and oport.
|
|
|
|
* @disable: disables flow between iport and oport.
|
|
|
|
*/
|
|
|
|
struct coresight_ops_link {
|
|
|
|
int (*enable)(struct coresight_device *csdev, int iport, int oport);
|
|
|
|
void (*disable)(struct coresight_device *csdev, int iport, int oport);
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct coresight_ops_source - basic operations for a source
|
|
|
|
* Operations available for sources.
|
2016-02-03 04:14:01 +07:00
|
|
|
* @cpu_id: returns the value of the CPU number this component
|
|
|
|
* is associated to.
|
2014-11-04 01:07:35 +07:00
|
|
|
* @trace_id: returns the value of the component's trace ID as known
|
2016-02-18 07:51:57 +07:00
|
|
|
* to the HW.
|
2015-10-07 22:26:39 +07:00
|
|
|
* @enable: enables tracing for a source.
|
2014-11-04 01:07:35 +07:00
|
|
|
* @disable: disables tracing for a source.
|
|
|
|
*/
|
|
|
|
struct coresight_ops_source {
|
2016-02-03 04:14:01 +07:00
|
|
|
int (*cpu_id)(struct coresight_device *csdev);
|
2014-11-04 01:07:35 +07:00
|
|
|
int (*trace_id)(struct coresight_device *csdev);
|
2016-02-18 07:51:57 +07:00
|
|
|
int (*enable)(struct coresight_device *csdev,
|
2016-08-26 04:19:10 +07:00
|
|
|
struct perf_event *event, u32 mode);
|
|
|
|
void (*disable)(struct coresight_device *csdev,
|
|
|
|
struct perf_event *event);
|
2014-11-04 01:07:35 +07:00
|
|
|
};
|
|
|
|
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
|
|
|
/**
|
|
|
|
* struct coresight_ops_helper - Operations for a helper device.
|
|
|
|
*
|
|
|
|
* All operations could pass in a device specific data, which could
|
|
|
|
* help the helper device to determine what to do.
|
|
|
|
*
|
|
|
|
* @enable : Enable the device
|
|
|
|
* @disable : Disable the device
|
|
|
|
*/
|
|
|
|
struct coresight_ops_helper {
|
|
|
|
int (*enable)(struct coresight_device *csdev, void *data);
|
|
|
|
int (*disable)(struct coresight_device *csdev, void *data);
|
|
|
|
};
|
|
|
|
|
2014-11-04 01:07:35 +07:00
|
|
|
struct coresight_ops {
|
|
|
|
const struct coresight_ops_sink *sink_ops;
|
|
|
|
const struct coresight_ops_link *link_ops;
|
|
|
|
const struct coresight_ops_source *source_ops;
|
coresight: Add helper device type
Add a new coresight device type, which do not belong to any
of the existing types, i.e, source, sink, link etc. A helper
device could be connected to a coresight device, which could
augment the functionality of the coresight device.
This is intended to cover Coresight Address Translation Unit (CATU)
devices, which provide improved Scatter Gather mechanism for TMC
ETR. The idea is that the helper device could be controlled by
the driver of the device it is attached to (in this case ETR),
transparent to the generic coresight driver (and paths).
The operations include enable(), disable(), both of which could
accept a device specific "data" which the driving device and
the helper device could share. Since they don't appear in the
coresight "path" tracked by software, we have to ensure that
they are powered up/down whenever the master device is turned
on.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-12 02:40:30 +07:00
|
|
|
const struct coresight_ops_helper *helper_ops;
|
2014-11-04 01:07:35 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_CORESIGHT
|
|
|
|
extern struct coresight_device *
|
|
|
|
coresight_register(struct coresight_desc *desc);
|
|
|
|
extern void coresight_unregister(struct coresight_device *csdev);
|
|
|
|
extern int coresight_enable(struct coresight_device *csdev);
|
|
|
|
extern void coresight_disable(struct coresight_device *csdev);
|
|
|
|
extern int coresight_timeout(void __iomem *addr, u32 offset,
|
|
|
|
int position, int value);
|
2018-09-21 02:18:11 +07:00
|
|
|
|
|
|
|
extern int coresight_claim_device(void __iomem *base);
|
|
|
|
extern int coresight_claim_device_unlocked(void __iomem *base);
|
|
|
|
|
|
|
|
extern void coresight_disclaim_device(void __iomem *base);
|
|
|
|
extern void coresight_disclaim_device_unlocked(void __iomem *base);
|
|
|
|
|
2014-11-04 01:07:35 +07:00
|
|
|
#else
|
|
|
|
static inline struct coresight_device *
|
|
|
|
coresight_register(struct coresight_desc *desc) { return NULL; }
|
|
|
|
static inline void coresight_unregister(struct coresight_device *csdev) {}
|
|
|
|
static inline int
|
|
|
|
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
|
|
|
|
static inline void coresight_disable(struct coresight_device *csdev) {}
|
|
|
|
static inline int coresight_timeout(void __iomem *addr, u32 offset,
|
|
|
|
int position, int value) { return 1; }
|
2018-09-21 02:18:11 +07:00
|
|
|
static inline int coresight_claim_device_unlocked(void __iomem *base)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int coresight_claim_device(void __iomem *base)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void coresight_disclaim_device(void __iomem *base) {}
|
|
|
|
static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
|
|
|
|
|
2015-01-10 06:57:20 +07:00
|
|
|
#endif
|
|
|
|
|
2014-11-04 01:07:35 +07:00
|
|
|
#ifdef CONFIG_OF
|
2017-06-06 03:15:15 +07:00
|
|
|
extern int of_coresight_get_cpu(const struct device_node *node);
|
2017-06-06 03:15:06 +07:00
|
|
|
extern struct coresight_platform_data *
|
|
|
|
of_get_coresight_platform_data(struct device *dev,
|
|
|
|
const struct device_node *node);
|
2015-01-10 06:57:20 +07:00
|
|
|
#else
|
2017-06-06 03:15:15 +07:00
|
|
|
static inline int of_coresight_get_cpu(const struct device_node *node)
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{ return 0; }
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2014-11-04 01:07:35 +07:00
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static inline struct coresight_platform_data *of_get_coresight_platform_data(
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2017-06-06 03:15:06 +07:00
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struct device *dev, const struct device_node *node) { return NULL; }
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2014-11-04 01:07:35 +07:00
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#endif
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#endif
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