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59 lines
3.1 KiB
Plaintext
59 lines
3.1 KiB
Plaintext
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1. stiH display hardware IP
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---------------------------
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The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
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- The High Quality Video Display Processor (HQVDP) gets video frames from a
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video decoder and does high quality video processing, including scaling.
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- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
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has several inputs:
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- The graphics planes are internally processed by the Generic Display
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Pipeline (GDP).
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- The video plug (VID) connects to the HQVDP output.
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- The cursor handles ... a cursor.
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- The TV OUT pre-formats (convert, clip, round) the compositor output data
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- The HDMI / DVO / HD Analog / SD analog IP builds the video signals
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- DVO (Digital Video Output) handles a 24bits parallel signal
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- The HD analog signal is typically driven by a YCbCr cable, supporting up to
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1080i mode.
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- The SD analog signal is typically used for legacy TV
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- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
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Note that some stiH drivers support only a subset of thee HW IP.
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.-------------. .-----------. .-----------.
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GPU >-------------+GDP Main | | +---+ HDMI +--> HDMI
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GPU >-------------+GDP mixer+---+ | :===========:
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GPU >-------------+Cursor | | +---+ DVO +--> 24b//
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------- | COMPOSITOR | | TV OUT | :===========:
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| | | | | +---+ HD analog +--> YCbCr
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Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
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dec | | | mixer| | +---+ SD analog +--> CVBS
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'-------' '-------------' '-----------' '-----------'
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.-----------.
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| main+--> Vsync
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| VTG |
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| aux+--> Vsync
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'-----------'
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2. DRM / HW mapping
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-------------------
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These IP are mapped to the DRM objects as following:
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- The CRTCs are mapped to the Compositor Main and Aux Mixers
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- The Framebuffers and planes are mapped to the Compositor GDP (non video
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buffers) and to HQVDP+VID (video buffers)
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- The Cursor is mapped to the Compositor Cursor
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- The Encoders are mapped to the TVOut
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- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
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FB & planes Cursor CRTC Encoders Bridges/Connectors
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| .-------------. | .-----------. .-----------. |
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+------------> |GDP | Main | | | +-> | | HDMI | <-+
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+------------> |GDP v mixer|<+ | | | :===========: |
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| |Cursor | | | +-> | | DVO | <-+
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| ------- | COMPOSITOR | | |TV OUT | | :===========: |
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| | | | | | | +-> | | HD analog | <-+
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+-> | HQVDP | |VID Aux |<+ | | | :===========: |
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| | | mixer| | +-> | | SD analog | <-+
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'-------' '-------------' '-----------' '-----------'
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